公开(公告)号：US20120052600A1

公开(公告)日：2012-03-01

申请号：US13217736

申请日：2011-08-25

申请人： Masaki Kamimura ,  Takashi Shimizu ,  Kunihiro Miyazaki

发明人： Masaki Kamimura ,  Takashi Shimizu ,  Kunihiro Miyazaki

IPC分类号： H01L21/66 ,  H01L21/306 ,  B65D85/86 ,  B05C11/00

CPC分类号： H01L22/20 ,  G05B19/41875 ,  G05B2219/32194 ,  G05B2219/32198 ,  G05B2219/45031 ,  Y02P90/22

摘要： A manufacturing method for a semiconductor device, comprising: performing first processing on a plurality of wafers in a first processing order in a first processing apparatus; obtaining a processed amount with respect to each of the plurality of wafers in the first processing; obtaining a processed amount with respect to each of the plurality of wafers by second processing in a second processing apparatus after the first processing; deciding a second processing order, which is different from the first processing order, from the processed amount with respect to each of the plurality of wafers by the first processing and the processed amount with respect to each of the plurality of wafers by the second processing; and performing the second processing on the plurality of wafers in the second processing order in the second processing apparatus.

摘要翻译： 一种半导体器件的制造方法，包括：在第一处理装置中以第一处理顺序对多个晶片执行第一处理; 在所述第一处理中获得关于所述多个晶片中的每一个的处理量; 通过在第一处理之后的第二处理装置中的第二处理来获得关于多个晶片中的每一个的处理量; 通过所述第一处理，通过所述第一处理和相对于所述多个晶片中的每一个处理的量，通过所述第二处理来确定与所述第一处理顺序不同的第二处理顺序相对于所述多个晶片中的每一个的处理量; 以及在所述第二处理装置中以所述第二处理顺序对所述多个晶片执行所述第二处理。

公开(公告)号：US20100169036A1

公开(公告)日：2010-07-01

申请号：US12365445

申请日：2009-02-04

申请人： Douglas Edmund Paradis ,  Karl Lynn Kenney

发明人： Douglas Edmund Paradis ,  Karl Lynn Kenney

IPC分类号： G06F19/00

CPC分类号： G05B19/41875 ,  B07C5/344 ,  G01R31/2894 ,  G05B2219/32198 ,  G05B2219/37097 ,  G05B2219/45031 ,  Y02P90/22

摘要： One embodiment relates to a computer method for aligning wafers processed in a semiconductor fabrication facility. In the method, a first arrangement of dies having a common functionality level is identified on a first wafer. A first alignment signature is assigned to the first wafer based on the first arrangement. A second arrangement of dies having the common functionality level is identified on a second wafer. A second alignment signature is assigned to the second wafer based on the second arrangement. The first alignment signature is compared to the second alignment signature, and the first and second wafers are selectively aligned based on a result of the comparison. Other systems and methods are also disclosed.

摘要翻译： 一个实施例涉及一种用于对准在半导体制造设备中处理的晶片的计算机方法。 在该方法中，在第一晶片上识别具有共同功能级别的管芯的第一布置。 基于第一布置将第一对准签名分配给第一晶片。 在第二晶片上识别具有共同功能级别的芯片的第二布置。 基于第二布置将第二对准签名分配给第二晶片。 将第一对准签名与第二对准签名进行比较，并且基于比较的结果来选择性地对准第一和第二晶片。 还公开了其它系统和方法。

公开(公告)号：US20060161288A1

公开(公告)日：2006-07-20

申请号：US11305074

申请日：2005-12-19

申请人： Shinichi Imai

发明人： Shinichi Imai

IPC分类号： G06F19/00

CPC分类号： G05B19/41835 ,  G05B2219/32057 ,  G05B2219/32058 ,  G05B2219/32096 ,  G05B2219/32135 ,  G05B2219/32198 ,  G05B2219/37224 ,  Y02P90/12 ,  Y02P90/18 ,  Y02P90/185 ,  Y02P90/20 ,  Y02P90/22

摘要： A method for manufacturing a semiconductor device is provided in which it is possible to perform process control taking account of wafer information and to deal with the process control in which a recipe is change from one wafer to another. The method comprises steps of inserting a process control system into the path of a network where a manufacturing execution system (MES) and a manufacturing apparatus are connected with each other by using a LAN, obtaining a process result on the lot of the wafers at a previous step through the use of the process control system to rewrite the process recipe, and transmitting the rewritten process recipe from the process control system to the manufacturing apparatus. Since the method includes the step of obtaining the process result on the lot effected at the previous step as wafer information, it is possible to calculate a control parameter taking account of the state of the wafers. Also, since a process control (APC) system is inserted between the MES and the apparatus, there is no communication between the MES and the APC system, so that a communication burden is reduced, thereby the process control can be performed from one wafer to another.

摘要翻译： 提供一种制造半导体器件的方法，其中可以考虑晶片信息进行处理控制，并且处理其中配方从一个晶片改变到另一个晶片的处理控制。 该方法包括以下步骤：通过使用LAN将制造执行系统（MES）和制造装置彼此连接的网络的路径插入到步骤S中，从而获得晶片批次的处理结果 上一步通过使用过程控制系统重写过程配方，并将重写过程配方从过程控制系统传送到制造设备。 由于该方法包括以上述步骤获得作为晶片信息的批次的处理结果的步骤，因此可以考虑晶片的状态来计算控制参数。 另外，由于在MES和装置之间插入了过程控制（APC）系统，所以在MES和APC系统之间不存在通信，从而减少了通信负担，从而可以从一个晶片到 另一个。

公开(公告)号：US20090132078A1

公开(公告)日：2009-05-21

申请号：US11874626

申请日：2007-10-18

申请人： Shinji SAKANO

发明人： Shinji SAKANO

IPC分类号： G06F19/00

CPC分类号： G05B19/41875 ,  G05B2219/32097 ,  G05B2219/32182 ,  G05B2219/32198 ,  G05B2219/37575 ,  G05B2219/37576 ,  G05B2219/45031 ,  H01L21/32135 ,  Y02P90/20 ,  Y02P90/22

摘要： A target value that serves as a control value with feed forward control is optimized. A TL performs a feed forward and a feedback control of a PM. A storage unit stores a plurality of recipes indicating different processing sequences, and a target value that serves as a control value when performing an etching process. A communication unit causes an IMM to measure a processing state of the wafer and receives measurement information. A computation unit computes a feedback value for the current wafer processed in the current cycle, based on pre-processing and post-processing measurement information for the wafer. An update unit updates the target value using the feedback value. A recipe adjustment unit changes the recipe to change the process performed in the same PM. When the process is performed after changing, the updated target value is used to perform feed forward control of the wafer in the same PM.

摘要翻译： 作为具有前馈控制的控制值的目标值被优化。 TL执行PM的前馈和反馈控制。 存储单元存储指示不同处理顺序的多个配方，以及当执行蚀刻处理时用作控制值的目标值。 通信单元使IMM测量晶片的处理状态并接收测量信息。 计算单元基于晶片的预处理和后处理测量信息来计算当前周期中处理的当前晶片的反馈值。 更新单元使用反馈值更新目标值。 配方调整单元更改配方以更改在同一个PM中执行的过程。 当改变之后执行处理时，更新的目标值被用于在相同的PM中执行晶片的前馈控制。

公开(公告)号：US20080140590A1

公开(公告)日：2008-06-12

申请号：US11609368

申请日：2006-12-12

申请人： Hsueh-Chi Shen

发明人： Hsueh-Chi Shen

IPC分类号： G06F15/18 ,  G06F17/00

CPC分类号： G05B19/41875 ,  G05B2219/32182 ,  G05B2219/32198 ,  G05B2219/35499 ,  G05B2219/45031 ,  Y02P90/22

摘要： Systems of process control integration are provided. An embodiment of a system of process control integration comprises multiple process control systems (PCSs) and a supervisor controller. Each PCS calculates at least one process parameter based on at least one process model, a process target and an acceptable range. The supervisor controller couples to and coordinates the PCSs. A semiconductor fabrication operation is performed on a wafer based on the process parameter.

摘要翻译： 提供过程控制集成系统。 过程控制集成系统的实施例包括多个过程控制系统（PCS）和主管控制器。 每个PCS基于至少一个过程模型，过程目标和可接受的范围来计算至少一个过程参数。 主管控制器耦合到PCS并协调PCS。 基于工艺参数在晶片上进行半导体制造操作。

公开(公告)号：US07324866B2

公开(公告)日：2008-01-29

申请号：US11305074

申请日：2005-12-19

申请人： Shinichi Imai

发明人： Shinichi Imai

IPC分类号： G06F19/00

CPC分类号： G05B19/41835 ,  G05B2219/32057 ,  G05B2219/32058 ,  G05B2219/32096 ,  G05B2219/32135 ,  G05B2219/32198 ,  G05B2219/37224 ,  Y02P90/12 ,  Y02P90/18 ,  Y02P90/185 ,  Y02P90/20 ,  Y02P90/22

摘要： A method for manufacturing a semiconductor device is provided in which it is possible to perform process control taking account of wafer information and to deal with the process control in which a recipe is change from one wafer to another. The method comprises steps of inserting a process control system into the path of a network where a manufacturing execution system (MES) and a manufacturing apparatus are connected with each other by using a LAN, obtaining a process result on the lot of the wafers at a previous step through the use of the process control system to rewrite the process recipe, and transmitting the rewritten process recipe from the process control system to the manufacturing apparatus. Since the method includes the step of obtaining the process result on the lot effected at the previous step as wafer information, it is possible to calculate a control parameter taking account of the state of the wafers. Also, since a process control (APC) system is inserted between the MES and the apparatus, there is no communication between the MES and the APC system, so that a communication burden is reduced, thereby the process control can be performed from one wafer to another.

摘要翻译： 提供一种制造半导体器件的方法，其中可以考虑晶片信息进行处理控制，并且处理其中配方从一个晶片改变到另一个晶片的处理控制。 该方法包括以下步骤：通过使用LAN将制造执行系统（MES）和制造装置彼此连接的网络的路径插入到步骤S中，从而获得晶片批次的处理结果 上一步通过使用过程控制系统重写过程配方，并将重写过程配方从过程控制系统传送到制造设备。 由于该方法包括以上述步骤获得作为晶片信息的批次的处理结果的步骤，因此可以考虑晶片的状态来计算控制参数。 另外，由于在MES和装置之间插入了过程控制（APC）系统，所以在MES和APC系统之间不存在通信，从而减少了通信负担，从而可以从一个晶片到 另一个。

公开(公告)号：US06604012B1

公开(公告)日：2003-08-05

申请号：US09644294

申请日：2000-08-23

申请人： Dae-Sik Cho ,  Hee-Sun Chae ,  Seok-Hyun Kim ,  Seung-Hoon Tong ,  Tae-Yang Yoon ,  Doh-Soon Kwak ,  Hee-Se Kang ,  Yll-Seug Park ,  Jae-Seok Oh

发明人： Dae-Sik Cho ,  Hee-Sun Chae ,  Seok-Hyun Kim ,  Seung-Hoon Tong ,  Tae-Yang Yoon ,  Doh-Soon Kwak ,  Hee-Se Kang ,  Yll-Seug Park ,  Jae-Seok Oh

IPC分类号： G06F1900

CPC分类号： G05B19/41875 ,  G05B2219/32077 ,  G05B2219/32198 ,  G05B2219/32263 ,  G05B2219/45031 ,  Y02P90/12 ,  Y02P90/20 ,  Y02P90/22

摘要： A lot dispatching method and system for variably applying the most suitable processing equipment and/or processing condition in a succeeding process of a semiconductor manufacturing process, wherein the succeeding process is influenced by the result of a preceding process. A lot processed by the preceding process is dispatched to the succeeding processing equipment according to a systematic analysis result obtained from a relationship between a process result of the preceding process and an efficiency and the characteristics of a plurality of processing equipment in the succeeding process. A plurality of process conditions for the succeeding process corresponding to the performance of the preceding process is provided. A respective process condition has characteristics that minimize the difference in performance in the succeeding process from a desired or target performance. By systematically analyzing the quality of the lot waiting to be dispatched, the succeeding process is performed with the most suitable process condition.

摘要翻译： 用于在半导体制造过程的后续过程中可变地应用最合适的处理设备和/或处理条件的大量调度方法和系统，其中后续处理受到前一处理的结果的影响。 根据从前一处理的处理结果与效率之间的关系获得的系统分析结果和后续处理中的多个处理设备的特性，将由前述处理进行的许多处理分派到后续处理设备。 提供了与前述处理的执行相对应的用于后续处理的多个处理条件。 相应的处理条件具有使从后续处理中的性能与期望性能或目标性能的差异最小化的特征。 通过系统地分析等待发送的批次的质量，以最合适的处理条件进行后续处理。

公开(公告)号：US08406911B2

公开(公告)日：2013-03-26

申请号：US12837910

申请日：2010-07-16

申请人： Shreyas Subhash Limaye ,  Andrew Crehan Walker ,  Yeheyis Workeneh

发明人： Shreyas Subhash Limaye ,  Andrew Crehan Walker ,  Yeheyis Workeneh

IPC分类号： G06F19/00

CPC分类号： G05B19/41875 ,  G05B2219/32017 ,  G05B2219/32198 ,  G05B2219/32416 ,  G05B2219/45031 ,  Y02P90/22 ,  Y02P90/86

摘要： A method and apparatus are provided for implementing Advanced Process Control (APC) for enhanced electrical, magnetic, or physical properties process output control using a sequential segmented interleaving algorithm. The sequential segmented interleaving algorithm includes two tuning equations running in parallel. A deposition time is calculated after a production run based upon the relationship between the electrical, magnetic, or physical properties process output and deposition time process input. A deposition rate offset value is calculated after a calibration run based upon the relationship between a calibration deposition thickness process output and an updated deposition time process input calculated after a last production run.

摘要翻译： 提供了一种方法和装置，用于实现使用顺序分段交织算法的增强电，磁或物理属性过程输出控制的高级过程控制（APC）。 顺序分段交织算法包括并行运行的两个调谐方程。 基于电气，磁性或物理性能过程输出与沉积时间过程输入之间的关系，在生产运行后计算沉积时间。 基于校准沉积厚度过程输出和在最后生产运行之后计算的更新的沉积时间过程输入之间的关系，在校准运行之后计算沉积速率偏移值。

公开(公告)号：US20130029434A1

公开(公告)日：2013-01-31

申请号：US13555375

申请日：2012-07-23

申请人： Jang-Sun KIM

发明人： Jang-Sun KIM

IPC分类号： H01L21/66

CPC分类号： G05B19/41875 ,  G05B2219/32198 ,  H01L22/20 ,  Y02P90/22

摘要： A method of fabricating a semiconductor device includes performing a first period of operation and a second period of operation at first equipment and second equipment. The first period of operation includes performing a first patterning process at each of the first equipment and the second equipment, generating first inspection data of the first equipment and first inspection data of the second equipment, generating first differential data of the second equipment including differentials of the first inspection data of the first equipment and the first inspection data of the second equipment, and calibrating a configuration of the second equipment with reference to the first differential data of the second equipment.

摘要翻译： 制造半导体器件的方法包括在第一设备和第二设备处执行第一操作周期和第二操作周期。 第一操作周期包括在第一设备和第二设备中的每一个处执行第一图案化处理，生成第一设备的第一检查数据和第二设备的第一检查数据，生成第二设备的第一差分数据，包括差分 第一设备的第一检查数据和第二设备的第一检查数据，并且参考第二设备的第一差分数据来校准第二设备的配置。

公开(公告)号：US20120016499A1

公开(公告)日：2012-01-19

申请号：US12837910

申请日：2010-07-16

申请人： Shreyas Subhash Limaye ,  Andrew Crehan Walker ,  Yeheyis Workeneh

发明人： Shreyas Subhash Limaye ,  Andrew Crehan Walker ,  Yeheyis Workeneh

IPC分类号： G05B19/00

CPC分类号： G05B19/41875 ,  G05B2219/32017 ,  G05B2219/32198 ,  G05B2219/32416 ,  G05B2219/45031 ,  Y02P90/22 ,  Y02P90/86

摘要： A method and apparatus are provided for implementing Advanced Process Control (APC) for enhanced electrical, magnetic, or physical properties process output control using a sequential segmented interleaving algorithm. The sequential segmented interleaving algorithm includes two tuning equations running in parallel. A deposition time is calculated after a production run based upon the relationship between the electrical, magnetic, or physical properties process output and deposition time process input. A deposition rate offset value is calculated after a calibration run based upon the relationship between a calibration deposition thickness process output and an updated deposition time process input calculated after a last production run.

摘要翻译： 提供了一种方法和装置，用于实现使用顺序分段交织算法的增强电，磁或物理属性过程输出控制的高级过程控制（APC）。 顺序分段交织算法包括并行运行的两个调谐方程。 基于电气，磁性或物理性能过程输出与沉积时间过程输入之间的关系，在生产运行后计算沉积时间。 基于校准沉积厚度过程输出和在最后生产运行之后计算的更新的沉积时间过程输入之间的关系，在校准运行之后计算沉积速率偏移值。