公开(公告)号：US10365447B2

公开(公告)日：2019-07-30

申请号：US15907543

申请日：2018-02-28

Applicant: Luxtera, Inc.

Inventor： Attila Mekis ,  Peter De Dobbelaere ,  Gianlorenzo Masini ,  Yannick De Koninck ,  Thierry Pinguet

IPC: H04B10/50 ,  G02B6/42 ,  H04B10/80 ,  G02B6/34 ,  G02B6/38 ,  G02B6/30 ,  G02B6/124

Abstract: Methods and systems for a chip-on-wafer-on-substrate assembly are disclosed and may include in an optical communication system comprising an electronics die and a substrate. The electronics die is bonded to a first surface of a photonic interposer and the substrate is coupled to a second surface of the photonic interposer opposite to the first surface. An optical fiber and a light source assembly are coupled to the second surface of the interposer in one or more cavities formed in the substrate. A continuous wave (CW) optical signal may be received in the photonic interposer from the light source assembly, and a modulated optical signal may be communicated between the optical fiber and photonic interposer. The received CW optical signal may be coupled to an optical waveguide in the photonic interposer using a grating coupler.

公开(公告)号：US20190162988A1

公开(公告)日：2019-05-30

申请号：US16267545

申请日：2019-02-05

Applicant: Luxtera, Inc.

Inventor： Ali Ayazi ,  Gianlorenzo Masini ,  Subal Sahni ,  Attila Mekis ,  Thierry Pinguet

IPC: G02F1/025 ,  G02F1/225

CPC classification number: G02F1/025 ,  G02F1/2257 ,  G02F2001/212 ,  G02F2201/06 ,  G02F2202/105

Abstract: Methods and systems for a low-parasitic silicon high-speed phase modulator are disclosed and may include in an optical phase modulator that comprises a PN junction waveguide formed in a silicon layer, wherein the silicon layer may be on an oxide layer and the oxide layer may be on a silicon substrate. The PN junction waveguide may have fingers of p-doped and n-doped regions on opposite sides along a length of the PN junction waveguide. Contacts may be formed on the fingers of p-doped and n-doped regions. The fingers of p-doped and n-doped regions may be arranged symmetrically about the PN junction waveguide or staggered along the length of the PN junction waveguide. Etch transition features may be removed along the p-doped and n-doped regions.

公开(公告)号：US10302880B2

公开(公告)日：2019-05-28

申请号：US16110587

申请日：2018-08-23

Applicant: Luxtera, Inc.

Inventor： Daniel Kucharski ,  John Andrew Guckenberger ,  Thierry Pinguet ,  Sherif Abdalla

IPC: G02B6/42

Abstract: A method and system for implementing high-speed electrical interfaces between semiconductor dies in optical communication systems are disclosed and may include communicating electrical signals between a first die and a second die via coupling pads which may be located in low impedance points in Tx and Rx paths. The electrical signals may be communicated via one or more current-mode, controlled impedance, and/or capacitively-coupled interfaces. The current-mode interface may include a cascode amplifier stage split between source and drain terminals of transistors on the dies. The controlled-impedance interfaces may include transmission line drivers on a first die and transmission lines on a second die. The capacitively-coupled interfaces may include capacitors formed by contact pads on the dies. The coupling pads may be connected via one or more of: wire bonds, metal pillars, solder balls, or conductive resin. The dies may comprise CMOS and may be coupled in a flip-chip configuration.

公开(公告)号：US10256908B2

公开(公告)日：2019-04-09

申请号：US14729826

申请日：2015-06-03

Applicant: Luxtera, Inc.

Inventor： Attila Mekis ,  Peter DeDobbelaere ,  Kosei Yokoyama ,  Sherif Abdalla ,  Steffen Gloeckner ,  John Guckenberger ,  Thierry Pinguet ,  Gianlorenzo Masini ,  Daniel Kucharski

IPC: H04B10/2575 ,  H04B10/40 ,  H01L21/84 ,  H01L27/12 ,  H01L27/06 ,  H01L25/16 ,  H01L25/065

Abstract: Methods and systems for monolithic integration of photonics and electronics in CMOS processes are disclosed and may include in an optoelectronic transceiver comprising photonic and electronic devices from two complementary metal-oxide semiconductor (CMOS) die with different silicon layer thicknesses for the photonic and electronic devices, the CMOS die bonded together by metal contacts: communicating optical signals and electronic signals to and from said optoelectronic transceiver utilizing a received continuous wave optical signal as a source signal. A first of the CMOS die includes the photonic devices and a second includes the electronic devices. Electrical signals may be communicated between electrical devices to the optical devices utilizing through-silicon vias coupled to the metal contacts. The metal contacts may include back-end metals from a CMOS process. The electronic and photonic devices may be fabricated on SOI wafers, with the SOI wafers being diced to form the CMOS die.

公开(公告)号：US09906304B2

公开(公告)日：2018-02-27

申请号：US15651952

申请日：2017-07-17

Applicant: Luxtera, Inc.

Inventor： Peter DeDobbelaere ,  Thierry Pinguet ,  Mark Peterson ,  Mark Harrison ,  Alexander G. Dickinson ,  Lawrence C. Gunn

IPC: G02B6/36 ,  H04B10/40 ,  G02B6/42 ,  G02B6/12 ,  G02B6/38

CPC classification number: H04B10/40 ,  G02B6/12004 ,  G02B6/3885 ,  G02B6/4214 ,  G02B6/4246 ,  G02B6/4295 ,  G02B2006/12121

Abstract: A transceiver comprising a chip, a semiconductor laser, and one or more photodetectors, the chip comprising optical and optoelectronic devices and electronic circuitry, where the transceiver is operable to: communicate, utilizing the semiconductor laser, an optical source signal into the chip via a light pipe with a sloped reflective surface, generate first optical signals in the chip based on the optical source signal, transmit the first optical signals from the chip via the light pipe, and receive second optical signals from the light pipe and converting the second optical signals to electrical signals via the photodetectors. The optical signals may be communicated out of and in to a top surface of the chip. The one or more photodetectors may be integrated in the chip. The optoelectronic devices may include the one or more photodetectors integrated in the chip. The light pipe may be a planar lightwave circuit (PLC).

公开(公告)号：US20160349450A1

公开(公告)日：2016-12-01

申请号：US15232067

申请日：2016-08-09

Applicant: Luxtera, Inc.

Inventor： Thierry Pinguet ,  Attila Mekis ,  Steffen Gloeckner

IPC: G02B6/124 ,  G02B6/34 ,  G02B6/30 ,  G02B6/12

CPC classification number: G02B6/124 ,  G01J1/02 ,  G01J1/0425 ,  G02B6/12004 ,  G02B6/30 ,  G02B6/34 ,  G02B6/4208 ,  G02B2006/12038 ,  G02B2006/12061 ,  G02B2006/12104 ,  G02B2006/12157

Abstract: A method and system for coupling optical signals into silicon optoelectronic chips are disclosed and may include coupling one or more optical signals into a back surface of a CMOS photonic chip comprising photonic, electronic, and optoelectronic devices. The devices may be integrated in a front surface of the chip and one or more optical couplers may receive the optical signals in the front surface of the chip. The optical signals may be coupled into the back surface of the chip via one or more optical fibers and/or optical source assemblies. The optical signals may be coupled to the grating couplers via a light path etched in the chip, which may be refilled with silicon dioxide. The chip may be flip-chip bonded to a packaging substrate. Optical signals may be reflected back to the grating couplers via metal reflectors, which may be integrated in dielectric layers on the chip.

Abstract translation: 公开了一种用于将光信号耦合到硅光电芯片的方法和系统，并且可以包括将一个或多个光信号耦合到包括光子，电子和光电器件的CMOS光子芯片的背表面中。 器件可以集成在芯片的前表面中，并且一个或多个光耦合器可以接收芯片前表面中的光信号。 光信号可以经由一个或多个光纤和/或光源组件耦合到芯片的后表面中。 光信号可以通过蚀刻在芯片中的光路耦合到光栅耦合器，其可以用二氧化硅再填充。 芯片可以倒装芯片结合到封装基板。 光信号可以经由金属反射器反射回光栅耦合器，金属反射器可以集成在芯片上的电介质层中。

公开(公告)号：US20150316793A1

公开(公告)日：2015-11-05

申请号：US14105527

申请日：2013-12-13

Applicant: Luxtera Inc.

Inventor： Ali Ayazi ,  Gianlorenzo Masini ,  Subal Sahni ,  Attila Mekis ,  Thierry Pinguet

IPC: G02F1/025 ,  G02F1/225

CPC classification number: G02F1/025 ,  G02F1/2257 ,  G02F2001/212 ,  G02F2201/06 ,  G02F2202/105

Abstract: Methods and systems for a low-parasitic silicon high-speed phase modulator are disclosed and may include fabricating an optical phase modulator that comprises a PN junction waveguide formed in a silicon layer, wherein the silicon layer may be on an oxide layer and the oxide layer may be on a silicon substrate. The PN junction waveguide may have p-doped and n-doped regions on opposite sides along a length of the PN junction waveguide, and portions of the p-doped and n-doped regions may be removed. Contacts may be formed on remaining portions of the p-doped and n-doped regions. Portions of the p-doped and n-doped regions may be removed symmetrically about the PN junction waveguide. Portions of the p-doped and n-doped regions may be removed in a staggered fashion along the length of the PN junction waveguide. Etch transition features may be removed along the p-doped and n-doped regions.

Abstract translation: 公开了一种用于低寄生硅高速相位调制器的方法和系统，并且可以包括制造包括形成在硅层中的PN结波导的光相位调制器，其中硅层可以在氧化物层上，氧化物层 可以在硅衬底上。 PN结波导可以在PN结波导的长度的相对侧上具有p掺杂区域和n掺杂区域，并且p掺杂区域和n掺杂区域的部分可以被去除。 可以在p掺杂区域和n掺杂区域的剩余部分上形成接触。 可以围绕PN结波导对称地去除部分p掺杂区域和n掺杂区域。 可以沿着PN结波导的长度以交错的方式去除部分p掺杂区域和n掺杂区域。 蚀刻跃迁特征可以沿着p掺杂区域和n掺杂区域去除。

公开(公告)号：USRE45390E1

公开(公告)日：2015-02-24

申请号：US13774808

申请日：2013-02-22

Applicant: Luxtera, Inc.

Inventor： Peter De Dobbelaere ,  Thierry Pinguet ,  Mark Peterson ,  Mark Harrison ,  Alexander G. Dickinson ,  Lawrence C. Gunn, III

IPC: G02B6/12 ,  G02B6/26 ,  H05K1/18

CPC classification number: H04B10/40 ,  G02B6/12004 ,  G02B6/3885 ,  G02B6/4214 ,  G02B6/4246 ,  G02B6/4295 ,  G02B2006/12121

Abstract: A transceiver comprising a CMOS chip and a laser coupled to the chip may be operable to communicate an optical source signal from a semiconductor laser into the CMOS chip. The optical source signal may be used to generate first optical signals that are transmitted from the CMOS chip to optical fibers coupled to the CMOS chip. Second optical signals may be received from the optical fibers and converted to electrical signals via photodetectors in the CMOS chip. The optical source signal may be communicated from the semiconductor laser into the CMOS chip via optical fibers in to a top surface and the first optical signals may be communicated out of a top surface of the CMOS chip. The optical source signal may be communicated into the CMOS chip and the first optical signals may be communicated from the CMOS chip via optical couplers, which may comprise grating couplers.

Abstract translation: 包括CMOS芯片和耦合到芯片的激光器的收发器可以用于将来自半导体激光器的光源信号传送到CMOS芯片。 光源信号可以用于产生从CMOS芯片发送到耦合到CMOS芯片的光纤的第一光信号。 可以从光纤接收第二光信号并且经由CMOS芯片中的光电检测器转换成电信号。 光源信号可以通过光纤从半导体激光器传送到CMOS芯片到顶表面，并且第一光信号可以从CMOS芯片的顶表面传出。 光源信号可以被传送到CMOS芯片，并且可以通过可以包括光栅耦合器的光耦合器从CMOS芯片传送第一光信号。

公开(公告)号：US20190293883A1

公开(公告)日：2019-09-26

申请号：US16424136

申请日：2019-05-28

Applicant: Luxtera, Inc.

Inventor： Daniel Kucharski ,  John Andrew Guckenberger ,  Thierry Pinguet ,  Sherif Abdalla

IPC: G02B6/42

Abstract: A method and system for implementing high-speed electrical interfaces between semiconductor dies in optical communication systems are disclosed and may include communicating electrical signals between a first die and a second die via coupling pads which may be located in low impedance points in Tx and Rx paths. The electrical signals may be communicated via one or more current-mode, controlled impedance, and/or capacitively-coupled interfaces. The current-mode interface may include a cascode amplifier stage split between source and drain terminals of transistors on the dies. The controlled-impedance interfaces may include transmission line drivers on a first die and transmission lines on a second die. The capacitively-coupled interfaces may include capacitors formed by contact pads on the dies. The coupling pads may be connected via one or more of: wire bonds, metal pillars, solder balls, or conductive resin. The dies may comprise CMOS and may be coupled in a flip-chip configuration.

公开(公告)号：US20190238228A1

公开(公告)日：2019-08-01

申请号：US16378119

申请日：2019-04-08

Applicant: Luxtera, Inc.

Inventor： Attila Mekis ,  Peter DeDobbelaere ,  Kosei Yokoyama ,  Sherif Abdalla ,  Steffen Gloeckner ,  John Guckenberger ,  Thierry Pinguet ,  Gianlorenzo Masini ,  Daniel Kucharski

IPC: H04B10/2575 ,  H01L27/12 ,  H04B10/40 ,  H01L21/84

CPC classification number: H04B10/2575 ,  H01L21/84 ,  H01L25/0652 ,  H01L25/167 ,  H01L27/0688 ,  H01L27/1203 ,  H01L2225/06541 ,  H04B10/40

Abstract: Methods and systems for monolithic integration of photonics and electronics in CMOS processes are disclosed and may include fabricating photonic and electronic devices on two CMOS wafers with different silicon layer thicknesses. The devices may be fabricated on semiconductor-on-insulator (SOI) wafers utilizing a bulk CMOS process and/or on a SOI wafer utilizing a SOI CMOS process. The different thicknesses may be fabricated utilizing a double SOI process and/or a selective area growth process. Cladding layers may be fabricated utilizing one or more oxygen implants and/or utilizing CMOS trench oxide on the CMOS wafer. Silicon may be deposited on the CMOS trench oxide utilizing epitaxial lateral overgrowth. Cladding layers may be fabricated utilizing selective backside etching. Reflective surfaces may be fabricated by depositing metal on the selectively etched regions. Silicon dioxide or silicon germanium integrated in the CMOS wafer may be utilized as an etch stop layer.