公开(公告)号：US12277346B2

公开(公告)日：2025-04-15

申请号：US18368292

申请日：2023-09-14

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shuo-Nan Hung ,  Nai-Ping Kuo ,  Chien-Hsin Liu

IPC: G06F3/06

Abstract: A memory system that is based on 3D NAND flash memory of a high capacity and/or capable of high performance is provided, which includes memory planes, each including a plane core and a specific set of resources. For each memory plane of the plurality of memory planes, the technology provides (i) a corresponding plane busy (PRDY) signal indicating a busy or a ready state of the specific set of recourses of the corresponding memory plane, and (ii) a corresponding plane in operation (PIO #) signal indicating an in operation or idle state of resources used by the plane core of the corresponding memory plane. Issuance of memory commands by a controller and execution of memory commands for a memory plane of the plurality of memory planes is selectively allowed or denied, based on status of one or more of the plurality of PRDY signals and the plurality of PIO # signals.

公开(公告)号：US20250087253A1

公开(公告)日：2025-03-13

申请号：US18464262

申请日：2023-09-11

Applicant: MACRONIX International Co., Ltd.

Inventor： Shuo-Nan Hung ,  Shih-Chou Juan ,  Chun-Lien Su

IPC: G11C7/10

Abstract: Disclosed are a multi-circuit control system and a reading method for status information thereof. The multi-circuit control system includes a first circuit and N second circuits. The second circuit is, for example a three dimensional NAND flash memory circuit, and the multi-circuit control system provides a storage media with high-performance and high-capacity. The first circuit provides a read clock signal. The second circuits are coupled in series, and coupled to the first circuit. Each of the second circuits has at least one first data shifter. The at least one data shifter is used to load status information of each of the second circuits, and shift out each of the status information to a second circuit of a previous stage or the first circuit or the first chip obtains the status information of each of the second circuits through a parallel transmission scheme.

公开(公告)号：US11853567B2

公开(公告)日：2023-12-26

申请号：US17953439

申请日：2022-09-27

Applicant: Macronix International Co., Ltd.

Inventor： Shuo-Nan Hung ,  E-Yuan Chang

IPC: G06F3/06

CPC classification number: G06F3/0632 ,  G06F3/0604 ,  G06F3/0619 ,  G06F3/0655 ,  G06F3/0679

Abstract: A memory controller accesses a memory page in a memory block of a storage memory array of a memory device. The memory controller reads memory data stored in the accessed memory page. The memory controller determines a number of error bits associated with the memory data. The memory controller obtains an erase count corresponding to the accessed memory page, the erase count indicating a number of erase operations performed on the accessed memory page. The memory controller determines, from among one or more error threshold values, an error threshold value based at least on the erase count. The memory controller determines a relationship between the number of error bits and the error threshold value. The memory controller triggers a data refresh for the accessed memory block if the relationship between the number of error bits and the error threshold value satisfy a known criterion.

公开(公告)号：US11550494B2

公开(公告)日：2023-01-10

申请号：US17166804

申请日：2021-02-03

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shuo-Nan Hung

IPC: G06F3/06

Abstract: A method provides the capability to maintain a configuration settings data image stored by a non-volatile memory device. The configuration settings data image can be multiple times programmed (MTP) without sacrificing reliability of the semiconductor device in the event of spurious power fluctuations, intermittent or bad memory storage blocks storing the configuration settings data image.

公开(公告)号：US11249913B2

公开(公告)日：2022-02-15

申请号：US17061451

申请日：2020-10-01

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shuo-Nan Hung ,  Chun-Lien Su

IPC: G06F12/08 ,  G06F12/0882

Abstract: A memory device includes a data register operatively coupled to the memory array, a cache operatively coupled to the data register, and an input/output interface operatively coupled to the cache. A controller executes a continuous page read operation to sequentially load pages to the data register and move the pages to the cache, in response to a page read command, executes the cache read operation in response to a cache read command to move data from the cache to the input/output interface, and to stall moving of the data from the cache until a next cache read command, and terminates the continuous page read operation in response to a terminate command.

公开(公告)号：US09690650B2

公开(公告)日：2017-06-27

申请号：US13951130

申请日：2013-07-25

Applicant: Macronix International Co., Ltd.

Inventor： Yi-Ching Liu ,  Chi Lo ,  Shuo-Nan Hung ,  Chun-Hsiung Hung

IPC: G11C29/00 ,  G06F11/10 ,  G11B20/18 ,  G11C7/10

CPC classification number: G06F11/1044 ,  G06F11/1008 ,  G06F11/1068 ,  G11B20/1833 ,  G11C7/1006

Abstract: A device includes a memory array storing data and error correcting codes ECCs corresponding to the data, and a multi-level buffer structure between the memory array and an input/output data path. The memory array includes a plurality of data lines for page mode operations. The buffer structure includes a first buffer having storage cells connected to respective data lines in the plurality of data lines for a page of data, a second buffer coupled to the storage cells in the first buffer for storing at least one page of data, and a third buffer coupled to the second buffer and to the input/output data path. The device includes logic coupled to the multi-level buffer to perform a logical process over pages of data during movement between the memory array and the input/output path through the multi-level buffer for at least one of page read and page write operations.

公开(公告)号：US11755399B1

公开(公告)日：2023-09-12

申请号：US17752502

申请日：2022-05-24

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shuo-Nan Hung ,  Chun-Hsiung Hung

IPC: G06F11/07 ,  G06F11/10 ,  G06F3/06

CPC classification number: G06F11/076 ,  G06F3/065 ,  G06F3/0619 ,  G06F3/0656 ,  G06F11/1044 ,  G06F3/0685

Abstract: An IC is provided and includes a memory array, an address register holding at least one address of a securely stored file and configured to output three or more addresses of the securely stored filed and computation-in-memory (CIM) logic coupled with the memory array. The CIM logic is configured to perform a majority function on three or more bits of the securely stored file, wherein the three or more bits are redundantly stored in three or more different locations in the memory array and wherein the three locations are associated with the three or more addresses in the memory array.

公开(公告)号：US11630786B2

公开(公告)日：2023-04-18

申请号：US17321193

申请日：2021-05-14

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shuo-Nan Hung

IPC: G06F13/16 ,  G06F3/06 ,  G06F11/10 ,  G11C29/52

Abstract: A memory device such as a page mode NAND flash including a page buffer, and an input/output interface for I/O data units having an I/O width less than the page width supports continuous page read with non-sequential addresses. A controller controls a continuous page read operation to output a stream of pages at the I/O interface. The continuous read operation includes responding to a series of commands to output a continuous stream of pages. The series of commands including a first command and a plurality of intra-stream commands received before completing output of a preceding page in the stream. The first command includes an address to initiate the continuous page read operation, and at least one intra-stream command in the plurality of intra-stream commands includes a non-sequential address to provide the non-sequential page in the stream of pages.

公开(公告)号：US20230015202A1

公开(公告)日：2023-01-19

申请号：US17953439

申请日：2022-09-27

Applicant: Macronix International Co., Ltd.

Inventor： Shuo-Nan Hung ,  E-Yuan Chang

IPC: G06F3/06

Abstract: A memory controller accesses a memory page in a memory block of a storage memory array of a memory device. The memory controller reads memory data stored in the accessed memory page. The memory controller determines a number of error bits associated with the memory data. The memory controller obtains an erase count corresponding to the accessed memory page, the erase count indicating a number of erase operations performed on the accessed memory page. The memory controller determines, from among one or more error threshold values, an error threshold value based at least on the erase count. The memory controller determines a relationship between the number of error bits and the error threshold value. The memory controller triggers a data refresh for the accessed memory block if the relationship between the number of error bits and the error threshold value satisfy a known criterion.

公开(公告)号：US11455254B2

公开(公告)日：2022-09-27

申请号：US17118239

申请日：2020-12-10

Applicant: MACRONIX International Co., Ltd.

Inventor： Chun-Lien Su ,  Chun-Hsiung Hung ,  Shuo-Nan Hung

IPC: G06F12/0882 ,  G06F11/10 ,  G06F12/02 ,  G06F12/0862

Abstract: A flash memory system and a flash memory thereof are provided. The flash memory device includes a NAND flash memory and a control circuit. The NAND flash memory chip includes a cache memory, a page buffer; and an NAND flash memory array. The NAND flash memory array includes a plurality of pages, wherein each page includes a plurality of sub-pages, each sub-page has a sub-page length. The cache memory is composed of a plurality of sub cache and each sub cache corresponds to different pages of the NAND flash memory array. The page buffer is composed of a plurality of sub-page buffers and each sub-page buffer corresponds to different pages of the NAND flash memory array. The control circuit is coupled to the host and the NAND flash memory, and performs an access operation in units of one sub-page.