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公开(公告)号：US10719241B2
公开(公告)日：2020-07-21
申请号：US15990497
申请日：2018-05-25
Applicant: Micron Technology, Inc.
Inventor： Matthew David Rowley , David Matthew Springberg , Dustin James Carter
Abstract: Disclosed is a power management integrated circuit with embedded address resolution protocol functionality. In one embodiment, a device is disclosed comprising a data storage device; and an address resolution protocol (ARP) state machine communicatively coupled to the data storage device and included within a power management integrated circuit (PMIC), the ARP state machine configured to assign an address to the data storage device and validate requests for data stored in the data storage device received over a bus.
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公开(公告)号：US20220413749A1
公开(公告)日：2022-12-29
申请号：US17896914
申请日：2022-08-26
Applicant: Micron Technology, Inc.
Inventor： David Matthew Springberg
IPC: G06F3/06
Abstract: Various embodiments enable a memory sub-system to perform a read operation based on consolidated memory region description data, which can be generated based on a memory region description data (e.g., SGL) provided by a host system for the read operation.
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公开(公告)号：US20190107966A1
公开(公告)日：2019-04-11
申请号：US16211048
申请日：2018-12-05
Applicant: MICRON TECHNOLOGY, INC.
Inventor： David Matthew Springberg , Matthew David Rowley , Peter Edward Kaineg
Abstract: A solid-state drive (SSD) includes a connector communicatively coupling the SSD to a host device, a controller coupled to the connector, and a memory device. The SSD also include a regulator configured to receive an instruction to enter a low power mode of the SSD, enter the low power mode upon receipt of the instruction, receive an indication to exit the low power mode, and exit the low power mode upon receipt of the indication.
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公开(公告)号：US20170371574A1
公开(公告)日：2017-12-28
申请号：US15194202
申请日：2016-06-27
Applicant: MICRON TECHNOLOGY, INC.
Inventor： David Matthew Springberg , Matthew David Rowley , Peter Edward Kaineg
CPC classification number: G06F3/0625 , G06F3/0634 , G06F3/0688 , G06F13/1668 , G06F13/4068 , G06F13/4282 , G06F2213/0026 , G06F2213/0032 , Y02D10/14 , Y02D10/151 , Y02D10/154
Abstract: A solid-state drive (SSD) includes a connector communicatively coupling the SSD to a host device, a controller coupled to the connector, and a memory device. The SSD also include a regulator configured to receive an instruction to enter a low power mode of the SSD, enter the low power mode upon receipt of the instruction, receive an indication to exit the low power mode, and exit the low power mode upon receipt of the indication.
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公开(公告)号：US20220308959A1
公开(公告)日：2022-09-29
申请号：US17216087
申请日：2021-03-29
Applicant: Micron Technology, Inc.
Inventor： David Matthew Springberg
Abstract: A processing device receives a request to write data to a memory device. The processing device generates a codeword based on the data. The codeword comprises the data and error correction code. The processing device generates a compressed codeword by compressing the codeword. The processing device stores the compressed codeword on a page of the memory device.
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Patent Agency Ranking
公开(公告)号：US11449272B1
公开(公告)日：2022-09-20
申请号：US17196584
申请日：2021-03-09
Applicant: Micron Technology, Inc.
Inventor： David Matthew Springberg
IPC: G06F3/06
Abstract: Various embodiments enable a memory sub-system to perform a read operation based on consolidated memory region description data, which can be generated based on a memory region description data (e.g., SGL) provided by a host system for the read operation.
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公开(公告)号：US10891062B2
公开(公告)日：2021-01-12
申请号：US16211048
申请日：2018-12-05
Applicant: MICRON TECHNOLOGY, INC.
Inventor： David Matthew Springberg , Matthew David Rowley , Peter Edward Kaineg
Abstract: A solid-state drive (SSD) includes a connector communicatively coupling the SSD to a host device, a controller coupled to the connector, and a memory device. The SSD also include a regulator configured to receive an instruction to enter a low power mode of the SSD, enter the low power mode upon receipt of the instruction, receive an indication to exit the low power mode, and exit the low power mode upon receipt of the indication.
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8.发明申请公开(公告)号：US20200348856A1
公开(公告)日：2020-11-05
申请号：US16932116
申请日：2020-07-17
Applicant: Micron Technology, Inc.
Inventor： Matthew David Rowley , David Matthew Springberg , Dustin James Carter
Abstract: Disclosed is a power management integrated circuit with embedded address resolution protocol functionality. In one embodiment, a device is disclosed comprising a data storage device; and an address resolution protocol (ARP) state machine communicatively coupled to the data storage device and included within a power management integrated circuit (PMIC), the ARP state machine configured to assign an address to the data storage device and validate requests for data stored in the data storage device received over a bus.
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公开(公告)号：US12026395B2
公开(公告)日：2024-07-02
申请号：US17896914
申请日：2022-08-26
Applicant: Micron Technology, Inc.
Inventor： David Matthew Springberg
IPC: G06F3/06
CPC classification number: G06F3/0655 , G06F3/0604 , G06F3/0676 , G06F3/0679
Abstract: Various embodiments enable a memory sub-system to perform a read operation based on consolidated memory region description data, which can be generated based on a memory region description data (e.g., SGL) provided by a host system for the read operation.
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公开(公告)号：US20230195571A1
公开(公告)日：2023-06-22
申请号：US18110684
申请日：2023-02-16
Applicant: Micron Technology, Inc.
Inventor： David Matthew Springberg
CPC classification number: G06F11/1068 , G06F3/0608 , G06F3/0619 , G11C16/0483 , G06F3/0679 , G11C16/26 , G11C16/10 , G06F3/0659
Abstract: A processing device receives a request to write data to a memory device. The processing device generates a codeword based on the data. The codeword comprises the data and error correction code. The processing device generates a compressed codeword by compressing the codeword. The processing device stores the compressed codeword on a page of the memory device.
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