公开(公告)号：US12213317B2

公开(公告)日：2025-01-28

申请号：US18508875

申请日：2023-11-14

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  Indra V. Chary ,  Justin B. Dorhout ,  Jian Li ,  Haitao Liu ,  Paolo Tessariol

IPC: H10B43/27 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. The operative channel-material strings in the laterally-spaced memory blocks comprise part of a memory plane. An elevationally-extending wall is in the memory plane laterally-between immediately-laterally-adjacent of the memory blocks and that completely encircles an island that is laterally-between immediately-laterally-adjacent of the memory blocks in the memory plane. Other embodiments, including method are disclosed.

公开(公告)号：US11792991B2

公开(公告)日：2023-10-17

申请号：US17567287

申请日：2022-01-03

Applicant: Micron Technology, Inc.

Inventor： Paolo Tessariol ,  Justin B. Dorhout ,  Jian Li ,  Ryan L. Meyer

IPC: H01L21/768 ,  H01L23/522 ,  H10B43/27 ,  H01L23/528 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

CPC classification number: H10B43/27 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5283 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Insulative pillars are laterally-between and longitudinally-spaced-along immediately-laterally-adjacent of the memory blocks. The pillars are directly against conducting material of conductive lines in the conductive tiers. Other arrays, and methods, are disclosed.

公开(公告)号：US20230143406A1

公开(公告)日：2023-05-11

申请号：US18083412

申请日：2022-12-16

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  Indra V. Chary ,  Justin B. Dorhout ,  Jian Li ,  Haitao Liu ,  Paolo Tessariol

IPC: H10B43/27 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

CPC classification number: H10B43/27 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5283 ,  H01L21/76816 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. The operative channel-material strings in the laterally-spaced memory blocks comprise part of a memory plane. An elevationally-extending wall is in the memory plane laterally-between immediately-laterally-adjacent of the memory blocks and that completely encircles an island that is laterally-between immediately-laterally-adjacent of the memory blocks in the memory plane. Other embodiments, including method are disclosed.

公开(公告)号：US11244955B2

公开(公告)日：2022-02-08

申请号：US16550244

申请日：2019-08-25

Applicant: Micron Technology, Inc.

Inventor： Paolo Tessariol ,  Justin B. Dorhout ,  Jian Li ,  Ryan L. Meyer

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Insulative pillars are laterally-between and longitudinally-spaced-along immediately-laterally-adjacent of the memory blocks. The pillars are directly against conducting material of conductive lines in the conductive tiers. Other arrays, and methods, are disclosed.

公开(公告)号：US20210343640A1

公开(公告)日：2021-11-04

申请号：US17374634

申请日：2021-07-13

Applicant: Micron Technology, Inc.

Inventor： Vladimir Machkaoutsan ,  Pieter Blomme ,  Emilio Camerlenghi ,  Justin B. Dorhout ,  Jian Li ,  Ryan L. Meyer ,  Paolo Tessariol

IPC: H01L23/522 ,  H01L23/528 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11524 ,  H01L21/311

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. First dummy pillars in the memory blocks extend through at least a majority of the insulative tiers and the conductive tiers through which the channel-material strings extend. Second dummy pillars are laterally-between and longitudinally-spaced-along immediately-laterally-adjacent of the memory blocks. The second dummy pillars extend through at least a majority of the insulative tiers and the conductive tiers through which the operative channel-material strings extend laterally-between the immediately-laterally-adjacent memory blocks. Other embodiments, including method, are disclosed.

公开(公告)号：US10978427B2

公开(公告)日：2021-04-13

申请号：US16592420

申请日：2019-10-03

Applicant: Micron Technology, Inc.

Inventor： Jian Li ,  Steven K. Groothuis

IPC: H01L25/065 ,  H01L25/00 ,  H01L25/18 ,  G11C7/04 ,  H01L23/498 ,  H01L23/367 ,  H01L23/00

Abstract: Stacked semiconductor die assemblies having memory dies stacked between partitioned logic dies and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a first logic die, a second logic die, and a thermally conductive casing defining an enclosure. The stack of memory dies can be disposed within the enclosure and between the first and second logic dies.

公开(公告)号：US20210057439A1

公开(公告)日：2021-02-25

申请号：US16550244

申请日：2019-08-25

Applicant: Micron Technology, Inc.

Inventor： Paolo Tessariol ,  Justin B. Dorhout ,  Jian Li ,  Ryan L. Meyer

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Insulative pillars are laterally-between and longitudinally-spaced-along immediately-laterally-adjacent of the memory blocks. The pillars are directly against conducting material of conductive lines in the conductive tiers. Other arrays, and methods, are disclosed.

公开(公告)号：US10818681B2

公开(公告)日：2020-10-27

申请号：US16160342

申请日：2018-10-15

Applicant: Micron Technology Inc.

Inventor： Yi Hu ,  Jian Li ,  Lifang Xu ,  Xiaosong Zhang

IPC: H01L27/11565 ,  H01L21/768 ,  H01L27/11582

Abstract: In an example, a method of forming a stacked memory array includes, forming a termination structure passing through a stack of alternating first and second dielectrics in a first region of the stack; forming first and second sets of contacts through the stack of alternating first and second dielectrics in a second region of the stack concurrently with forming the termination structure; forming an opening through the stack of alternating first and second dielectrics between the first and second sets of contacts so that the opening terminates at the termination structure; and removing the first dielectrics from the second region by accessing the first dielectrics through the opening so that the first and second sets of contacts pass through the second dielectrics alternating with spaces corresponding to the removed first dielectrics.

公开(公告)号：US20200141658A1

公开(公告)日：2020-05-07

申请号：US16726735

申请日：2019-12-24

Applicant: Micron Technology, Inc.

Inventor： Steven K. Groothuis ,  Jian Li

IPC: F28D15/04 ,  F28D15/02 ,  H01L23/427 ,  H01L23/367

Abstract: Semiconductor device assemblies having stacked semiconductor dies and thermal transfer devices that include vapor chambers are disclosed herein. In one embodiment, a semiconductor device assembly includes a first semiconductor die, a second semiconductor die on a base region of the first die, and a thermal transfer device attached to a peripheral region of the first die and extending over the second die. The thermal transfer device includes a conductive structure having an internal cavity and a working fluid at least partially filling the cavity. The conductive structure further includes first and second fluid conversion regions adjacent the cavity. The first fluid conversion region transfers heat from at least the peripheral region of the first die to a volume of the working fluid to vaporize the volume in the cavity, and the second fluid conversion region condenses the volume of the working fluid in the cavity after it has been vaporized.

公开(公告)号：US10163830B2

公开(公告)日：2018-12-25

申请号：US15344893

申请日：2016-11-07

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jaspreet S. Gandhi ,  James M. Derderian ,  Sameer S. Vadhavkar ,  Jian Li

IPC: H01L23/16 ,  H01L23/00 ,  H01L23/48 ,  H01L23/367 ,  H01L23/34 ,  H01L21/78 ,  H01L25/065 ,  H01L25/00

Abstract: Apparatuses and methods for providing thermal pathways from a substrate to a thermal bonding pad. The thermal pathways may be metal extensions of the thermal bonding pad that are disposed in channels formed in a backside passivation layer underneath the thermal bonding pad, and may be in direct contact with an underlying substrate. The thermal pathways may provide improved thermal dissipation from the substrate.