公开(公告)号：US10985753B2

公开(公告)日：2021-04-20

申请号：US16229266

申请日：2018-12-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kenji Asaki ,  Shuichi Tsukada

IPC: H03K17/687 ,  G11C7/12

Abstract: Apparatuses and methods for providing bias signals in a semiconductor device are described. As example apparatus includes a power supply line configured to provide a supply voltage and further includes first and second nodes. An impedance element is coupled between the power supply line and the first node and a first transistor having a gate, a source coupled to the first node, and a drain coupled to the second node. A reference line is configured to provide a reference voltage. A second transistor has a gate, a source coupled to the reference line, and a drain. The gate and the drain of the second transistor are coupled to the gate of the first transistor.

公开(公告)号：US20200257331A1

公开(公告)日：2020-08-13

申请号：US16271679

申请日：2019-02-08

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kenji Asaki ,  Shuichi Tsukada

IPC: G06F1/08 ,  G06F1/28 ,  H03B5/12

Abstract: In some embodiments, clock input buffer circuitry and divider circuitry use a combination of externally-suppled voltages and internally-generated voltages to provide the various clock signals used by a semiconductor device. For example, a clock input buffer is configured to provide second complementary clock signals responsive to received first complementary clock signals using cross-coupled buffer circuitry coupled to a supply voltage and to drive the first complementary clock signals using driver circuitry coupled to an internal voltage. In another example, a divider circuitry may provide divided clock signals based on the second complementary clock signals via a divider coupled to the internal voltage and to drive the divided clock signals using driver circuitry coupled to the supply voltage. A magnitude of the supply voltage may be less than a magnitude of the internal voltage.

公开(公告)号：US20220011809A1

公开(公告)日：2022-01-13

申请号：US17486429

申请日：2021-09-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kenji Asaki ,  Shuichi Tsukada

IPC: G06F1/08 ,  H03B5/12 ,  G06F1/28

Abstract: In some embodiments, clock input buffer circuitry and divider circuitry use a combination of externally-suppled voltages and internally-generated voltages to provide the various clock signals used by a semiconductor device. For example, a clock input buffer is configured to provide second complementary clock signals responsive to received first complementary clock signals using cross-coupled buffer circuitry coupled to a supply voltage and to drive the first complementary clock signals using driver circuitry coupled to an internal voltage. In another example, a divider circuitry may provide divided clock signals based on the second complementary clock signals via a divider coupled to the internal voltage and to drive the divided clock signals using driver circuitry coupled to the supply voltage. A magnitude of the supply voltage may be less than a magnitude of the internal voltage.

公开(公告)号：US20230078117A1

公开(公告)日：2023-03-16

申请号：US17475206

申请日：2021-09-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kenji Asaki

IPC: G11C29/50 ,  G11C11/408

Abstract: Apparatuses including and methods for memory subword driver circuits with reduced gate induced drain leakage are described. An example apparatus includes a first subword line and a second subword line coupled to the first subword line by a first common transistor where, in response to a test mode signal, a voltage of each of the first and second subword lines is raised to a first voltage and a gate voltage of the first common transistor is raised to a second voltage. In another example apparatus first and second subword drivers are coupled to the first and second subword lines respectively, and a driver circuit is coupled to the first and second subword drivers. The driver circuit outputs a first high signal to cause the first and second subword lines to rise to the first voltage and the gate voltage of the first common transistor to rise to the second voltage.

公开(公告)号：US20220336007A1

公开(公告)日：2022-10-20

申请号：US17235775

申请日：2021-04-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kenji Asaki

IPC: G11C11/4091 ,  G11C11/4076

Abstract: An apparatus including a temperature dependent circuit is configured to receive a temperature dependent power supply voltage, and further is configured to receive a first input signal and provide a temperature dependent output signal responsive to the input signal. A power control circuit including the temperature dependent circuit is configured to receive a second input signal, and further configured provide a first control voltage based on the first temperature dependent output signal and provide a second control voltage based on the second input signal. The second control voltage has a temperature dependency based on the temperature dependent power supply voltage. A sense amplifier coupled to a pair of digit lines is configured to receive the first and second control voltages and amplify a voltage difference between the digit lines of the pair.

公开(公告)号：US11132015B2

公开(公告)日：2021-09-28

申请号：US16271679

申请日：2019-02-08

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kenji Asaki ,  Shuichi Tsukada

IPC: G06F1/08 ,  H03B5/12 ,  G06F1/28 ,  G06F1/06 ,  G06F13/16 ,  G06F13/00 ,  G06F1/04 ,  G06F1/10

Abstract: In some embodiments, clock input buffer circuitry and divider circuitry use a combination of externally-suppled voltages and internally-generated voltages to provide the various clock signals used by a semiconductor device. For example, a clock input buffer is configured to provide second complementary clock signals responsive to received first complementary clock signals using cross-coupled buffer circuitry coupled to a supply voltage and to drive the first complementary clock signals using driver circuitry coupled to an internal voltage. In another example, a divider circuitry may provide divided clock signals based on the second complementary clock signals via a divider coupled to the internal voltage and to drive the divided clock signals using driver circuitry coupled to the supply voltage. A magnitude of the supply voltage may be less than a magnitude of the internal voltage.

公开(公告)号：US10438650B1

公开(公告)日：2019-10-08

申请号：US16041480

申请日：2018-07-20

Applicant: Micron Technology, Inc.

Inventor： Akira Yamashita ,  Kenji Asaki

IPC: G11C11/4076 ,  G11C11/4093

Abstract: A memory device includes an internal storage unit configured to store mode data specifying an operating speed of the memory device; a control decoder coupled to the internal storage unit, the control decoder configured to generate a delay control signal based on the mode data; and an input buffer coupled to the control decoder, the input buffer configured to adjust a delay of an input signal based on the delay control signal.

公开(公告)号：US10199081B1

公开(公告)日：2019-02-05

申请号：US15833688

申请日：2017-12-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kenji Asaki ,  Shuichi Tsukada

IPC: H03B1/00 ,  G11C7/12 ,  H03K17/687

Abstract: Apparatuses and methods for providing bias signals in a semiconductor device are described. As example apparatus includes a power supply line configured to provide a supply voltage and further includes first and second nodes. An impedance element is coupled between the power supply line and the first node and a first transistor having a gate, a source coupled to the first node, and a drain coupled to the second node. A reference line is configured to provide a reference voltage. A second transistor has a gate, a source coupled to the reference line, and a drain. The gate and the drain of the second transistor are coupled to the gate of the first transistor.

公开(公告)号：US12046273B2

公开(公告)日：2024-07-23

申请号：US17936166

申请日：2022-09-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Akira Yamashita ,  Kenji Asaki

IPC: G11C11/4093 ,  G01R31/26 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076

CPC classification number: G11C11/4093 ,  G11C11/4076 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/1087 ,  G11C7/22 ,  G11C7/222 ,  G11C2207/2254

Abstract: Apparatuses and methods for saving power at an input buffer are described. An example apparatus includes an input buffer comprising an amplifier coupled to a pair of serially coupled inverters, and a de-emphasis circuit coupled to the input buffer in parallel with one of the pair of serially-coupled inverters. The de-emphasis circuit comprising a plurality of transistors coupled in parallel to a resistance. The example apparatus further includes an input buffer control circuit configured to selectively enable one of the plurality of transistors to adjust a gain across the one of the pair of inverters based on a latency setting.

公开(公告)号：US11709523B2

公开(公告)日：2023-07-25

申请号：US17486429

申请日：2021-09-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kenji Asaki ,  Shuichi Tsukada

IPC: G06F1/08 ,  H03B5/12 ,  G06F1/28 ,  G06F1/06 ,  G06F13/16 ,  G06F13/00 ,  G06F1/04 ,  G06F1/10

CPC classification number: G06F1/08 ,  G06F1/28 ,  H03B5/1209 ,  G06F1/04 ,  G06F1/06 ,  G06F1/10 ,  G06F13/00 ,  G06F13/1689

Abstract: In some embodiments, clock input buffer circuitry and divider circuitry use a combination of externally-suppled voltages and internally-generated voltages to provide the various clock signals used by a semiconductor device. For example, a clock input buffer is configured to provide second complementary clock signals responsive to received first complementary clock signals using cross-coupled buffer circuitry coupled to a supply voltage and to drive the first complementary clock signals using driver circuitry coupled to an internal voltage. In another example, a divider circuitry may provide divided clock signals based on the second complementary clock signals via a divider coupled to the internal voltage and to drive the divided clock signals using driver circuitry coupled to the supply voltage. A magnitude of the supply voltage may be less than a magnitude of the internal voltage.