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公开(公告)号：US10409506B2
公开(公告)日：2019-09-10
申请号：US16117348
申请日：2018-08-30
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Shafqat Ahmed , Khaled Hasnat , Pranav Kalavade , Krishna Parat , Aaron Yip , Mark A. Helm , Andrew Bicksler
IPC: G06F3/06 , G11C16/04 , G11C16/24 , G11C16/26 , G06F12/0804 , G06F13/28 , G06F12/0846
Abstract: Methods for programming sense flags may include programming memory cells coupled to first data lines in a main memory array, and programming memory cells coupled to second data lines in the main memory array while programming memory cells coupled to data lines in a flag memory array with flag data indicative of the memory cells coupled to the second data lines being programmed. Methods for sensing flags may include performing a sense operation on memory cells coupled to first data lines of a main memory array and memory cells coupled to data lines of a flag memory array, and determining a program indication of memory cells coupled to second data lines of the main memory array from the sense operation performed on the memory cells coupled to the data lines of the flag memory array.
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公开(公告)号：US20180322933A1
公开(公告)日：2018-11-08
申请号：US16035857
申请日：2018-07-16
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Akira Goda , Yijie Zhao , Krishna Parat
Abstract: Memory devices including a controller configured to cause the memory device to apply a positive first voltage level to a first data line selectively connected to a first string of series-connected memory cells while applying a second voltage level, higher than the first voltage level, to a second data line selectively connected to a second string of series-connected memory cells; while applying the first voltage level to the first data line and applying the second voltage level to the second data line, applying a third voltage level to a particular access line coupled to a memory cell of a first string of series-connected memory cells selected for programming, wherein a differential between the third voltage level and the first voltage level is configured to increase a threshold voltage of the memory cell selected for programming, as well as other apparatus containing similar memory devices.
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公开(公告)号：US09519582B2
公开(公告)日：2016-12-13
申请号：US14833175
申请日：2015-08-24
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Shafqat Ahmed , Khaled Hasnat , Pranav Kalavade , Krishna Parat , Aaron Yip , Mark A. Helm , Andrew Bicksler
CPC classification number: G06F3/0625 , G06F3/061 , G06F3/0653 , G06F3/0665 , G06F3/0688 , G06F3/0689 , G06F12/0804 , G06F12/0846 , G06F13/28 , G06F2212/2022 , G06F2212/224 , G06F2212/461 , G11C16/0483 , G11C16/24 , G11C16/26 , Y02D10/14
Abstract: Memory devices, methods for programming sense flags, methods for sensing flags, and memory systems are disclosed. In one such memory device, the odd bit lines of a flag memory cell array are connected with a short circuit to a dynamic data cache. The even bit lines of the flag memory cell array are disconnected from the dynamic data cache. When an even page of a main memory cell array is read, the odd flag memory cells, comprising flag data, are read at the same time so that it can be determined whether the odd page of the main memory cell array has been programmed. If the flag data indicates that the odd page has not been programmed, threshold voltage windows can be adjusted to determine the states of the sensed even memory cell page.
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公开(公告)号：US09437304B2
公开(公告)日：2016-09-06
申请号：US14857475
申请日：2015-09-17
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Akira Goda , Haitao Liu , Krishna Parat
IPC: G11C16/04 , G11C16/10 , H01L27/115
CPC classification number: G11C16/10 , G11C16/0483 , H01L27/11556 , H01L27/11582
Abstract: An embodiment of a method includes decreasing a difference of a voltage applied to a first select gate minus a voltage applied to a source while the first select gate is off, decreasing a difference of a voltage applied to a second select gate minus a voltage applied to a data line while the second select gate is off, and increasing a voltage of a signal applied to a selected access line that is coupled to an untargeted memory cell in a string of memory cells coupled to the first and second select gates to a program voltage after or substantially concurrently with decreasing the difference of the voltage applied to the first select gate minus the voltage applied to the source and with decreasing the difference of the voltage applied to the second select gate minus the voltage applied to the data line.
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公开(公告)号：US20180373451A1
公开(公告)日：2018-12-27
申请号：US16117348
申请日：2018-08-30
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Shafqat Ahmed , Khaled Hasnat , Pranav Kalavade , Krishna Parat , Aaron Yip , Mark A. Helm , Andrew Bicksler
IPC: G06F3/06 , G11C16/26 , G11C16/24 , G11C16/04 , G06F13/28 , G06F12/0846 , G06F12/0804
CPC classification number: G06F3/0625 , G06F3/061 , G06F3/0653 , G06F3/0665 , G06F3/0688 , G06F3/0689 , G06F12/0804 , G06F12/0846 , G06F13/28 , G06F2212/2022 , G06F2212/224 , G06F2212/461 , G11C16/0483 , G11C16/24 , G11C16/26 , Y02D10/14
Abstract: Methods for programming sense flags may include programming memory cells coupled to first data lines in a main memory array, and programming memory cells coupled to second data lines in the main memory array while programming memory cells coupled to data lines in a flag memory array with flag data indicative of the memory cells coupled to the second data lines being programmed. Methods for sensing flags may include performing a sense operation on memory cells coupled to first data lines of a main memory array and memory cells coupled to data lines of a flag memory array, and determining a program indication of memory cells coupled to second data lines of the main memory array from the sense operation performed on the memory cells coupled to the data lines of the flag memory array.
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Patent Agency Ranking
公开(公告)号：US10049756B2
公开(公告)日：2018-08-14
申请号：US15478312
申请日：2017-04-04
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Akira Goda , Yijie Zhao , Krishna Parat
Abstract: A first string of memory cells, including a selected memory cell, and a second string of memory cells are coupled to a common data line and a common source. The data line is biased to a first potential greater than a second potential to which the source is biased and a select gate coupled between the second string of memory cells and the data line is deactivated during a programming operation performed on the selected memory cell. The programming operation includes applying a programming potential to a control gate of the selected memory cell concurrently with biasing the data line to the first potential and biasing the source to the second potential while the select gate is deactivated.
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公开(公告)号：US20170206977A1
公开(公告)日：2017-07-20
申请号：US15478312
申请日：2017-04-04
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Akira Goda , Yijie Zhao , Krishna Parat
CPC classification number: G11C16/3427 , G11C16/0483 , G11C16/10 , G11C16/3418
Abstract: A first string of memory cells, including a selected memory cell, and a second string of memory cells are coupled to a common data line and a common source. The data line is biased to a first potential greater than a second potential to which the source is biased and a select gate coupled between the second string of memory cells and the data line is deactivated during a programming operation performed on the selected memory cell. The programming operation includes applying a programming potential to a control gate of the selected memory cell concurrently with biasing the data line to the first potential and biasing the source to the second potential while the select gate is deactivated.
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公开(公告)号：US20150363313A1
公开(公告)日：2015-12-17
申请号：US14833175
申请日：2015-08-24
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Shafqat Ahmed , Khaled Hasnat , Pranav Kalavade , Krishna Parat , Aaron Yip , Mark A. Helm , Andrew Bicksler
CPC classification number: G06F3/0625 , G06F3/061 , G06F3/0653 , G06F3/0665 , G06F3/0688 , G06F3/0689 , G06F12/0804 , G06F12/0846 , G06F13/28 , G06F2212/2022 , G06F2212/224 , G06F2212/461 , G11C16/0483 , G11C16/24 , G11C16/26 , Y02D10/14
Abstract: Memory devices, methods for programming sense flags, methods for sensing flags, and memory systems are disclosed. In one such memory device, the odd bit lines of a flag memory cell array are connected with a short circuit to a dynamic data cache. The even bit lines of the flag memory cell array are disconnected from the dynamic data cache. When an even page of a main memory cell array is read, the odd flag memory cells, comprising flag data, are read at the same time so that it can be determined whether the odd page of the main memory cell array has been programmed. If the flag data indicates that the odd page has not been programmed, threshold voltage windows can be adjusted to determine the states of the sensed even memory cell page.
Abstract translation: 公开了存储器件，用于编程感测标志的方法，用于感测标志的方法和存储器系统。 在一个这样的存储器件中，标志存储器单元阵列的奇数位线与短路连接到动态数据高速缓存。 标记存储单元阵列的偶数位线与动态数据高速缓存断开连接。 当读取主存储单元阵列的偶数页时，同时读取包括标志数据的奇数标志存储单元，以便可以确定主存储单元阵列的奇数页是否已被编程。 如果标志数据指示奇数页未被编程，则可以调整阈值电压窗口以确定感测到的偶数存储单元页的状态。
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公开(公告)号：US11029861B2
公开(公告)日：2021-06-08
申请号：US16543743
申请日：2019-08-19
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Shafqat Ahmed , Khaled Hasnat , Pranav Kalavade , Krishna Parat , Aaron Yip , Mark A. Helm , Andrew Bicksler
IPC: G06F3/06 , G11C16/24 , G11C16/26 , G11C16/04 , G06F12/0804 , G06F13/28 , G06F12/0846
Abstract: Memory devices might be configured to perform methods including reading a first page of memory cells and flag data wherein the flag data indicates whether a second page of memory cells adjacent to the first page is programmed, and determining from the flag data whether to re-read the first page of memory cells with an adjusted read voltage; performing a sense operation on memory cells coupled to first data lines of a first array of memory cells and memory cells coupled to data lines of a second array of memory cells, and determining a program indication of memory cells coupled to second data lines from the sense operation performed on the memory cells coupled to the data lines of the second array of memory cells; and/or programming memory cells coupled to first data lines in a first array of memory cells, and programming memory cells coupled to second data lines in the first array of memory cells while programming memory cells coupled to data lines in a second array of memory cells with flag data indicative of the memory cells coupled to the second data lines in the first array of memory cells being programmed.
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公开(公告)号：US20190295668A1
公开(公告)日：2019-09-26
申请号：US16435996
申请日：2019-06-10
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Akira Goda , Yijie Zhao , Krishna Parat
Abstract: Memory devices including a controller configured to cause the memory device to apply a positive first voltage level to a first data line selectively connected to a first string of series-connected memory cells while applying a second voltage level, higher than the first voltage level, to a second data line selectively connected to a second string of series-connected memory cells; while applying the first voltage level to the first data line and applying the second voltage level to the second data line, applying a third voltage level to a particular access line coupled to a memory cell of a first string of series-connected memory cells selected for programming, wherein a differential between the third voltage level and the first voltage level is configured to increase a threshold voltage of the memory cell selected for programming, as well as other apparatus containing similar memory devices.
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