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    Semiconductor constructions
    1.
    发明授权
    Semiconductor constructions 有权

    公开(公告)号：US10014301B2

    公开(公告)日：2018-07-03

    申请号：US14848115

    申请日：2015-09-08

    Applicant: Micron Technology, Inc.

    Inventor： Mark Kiehlbauch

    IPC: H01L27/108 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/78 ,  H01L23/528 ,  H01L23/535

    CPC classification number: H01L27/10808 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823475 ,  H01L23/528 ,  H01L23/535 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Some embodiments include methods in which a pair of spaced-apart adjacent features is formed over a substrate. The features have silicon dioxide surfaces. Silicon nitride is deposited between the features. A first region of the silicon nitride is protected with a mask while a second region is not. The second region is removed to form an opening between the features. Some embodiments include semiconductor constructions that contain a pair of spaced-apart adjacent features. The features are lines extending along a first direction, and are spaced from one another by a trench. Alternating plugs and intervening materials are within the trench, with the plugs and intervening materials alternating along the first direction. The intervening materials consist of silicon nitride, and the plugs have lateral peripheries that directly contact silicon dioxide of the features, and that directly contact silicon nitride of the intervening regions.

    APPARATUS AND METHODS FOR CAPACITIVELY COUPLED PLASMA VAPOR PROCESSING OF SEMICONDUCTOR WAFERS
    2.
    发明申请
    APPARATUS AND METHODS FOR CAPACITIVELY COUPLED PLASMA VAPOR PROCESSING OF SEMICONDUCTOR WAFERS 有权
    用于电容耦合等离子体蒸汽处理半导体波形的装置和方法

    公开(公告)号：US20130154479A1

    公开(公告)日：2013-06-20

    申请号：US13767526

    申请日：2013-02-14

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Mark Kiehlbauch

    IPC: H01J1/13

    CPC classification number: H01J1/135 ,  H01J37/32091 ,  H01J37/32724 ,  H01L21/67069 ,  H01L21/67109

    Abstract: A capacitively coupled plasma reactor comprising a processing chamber, a first electrode, a second electrode and a thermoelectric unit. The processing chamber has an upper portion with a gas inlet and a lower portion, and the upper portion is in fluid communication with the lower portion. The first electrode has a front side and a backside and is positioned at the upper portion of the processing chamber. The second electrode is positioned in the lower portion of the processing chamber and is spaced apart from the front side of the first electrode. The thermoelectric unit is positioned proximate to the backside of the first electrode and is capable of heating and cooling the first electrode.

    Abstract translation: 一种电容耦合等离子体反应器，包括处理室，第一电极，第二电极和热电单元。 处理室具有上部，其具有气体入口和下部，并且上部与下部流体连通。 第一电极具有前侧和后侧，并且位于处理室的上部。 第二电极位于处理室的下部并且与第一电极的前侧间隔开。 热电单元位于第一电极的后侧附近并且能够加热和冷却第一电极。

    Semiconductor Constructions, and Semiconductor Processing Methods
    4.
    发明申请
    Semiconductor Constructions, and Semiconductor Processing Methods 审中-公开

    公开(公告)号：US20180286865A1

    公开(公告)日：2018-10-04

    申请号：US15995648

    申请日：2018-06-01

    Applicant: Micron Technology, Inc.

    Inventor： Mark Kiehlbauch

    IPC: H01L27/108 ,  H01L21/768 ,  H01L29/78 ,  H01L23/535 ,  H01L23/528 ,  H01L21/8234

    Abstract: Some embodiments include methods in which a pair of spaced-apart adjacent features is formed over a substrate. The features have silicon dioxide surfaces. Silicon nitride is deposited between the features. A first region of the silicon nitride is protected with a mask while a second region is not. The second region is removed to form an opening between the features. Some embodiments include semiconductor constructions that contain a pair of spaced-apart adjacent features. The features are lines extending along a first direction and are spaced from one another by a trench. Alternating plugs and intervening materials are within the trench, with the plugs and intervening materials alternating along the first direction. The intervening materials consist of silicon nitride, and the plugs have lateral peripheries that directly contact silicon dioxide of the features, and that directly contact silicon nitride of the intervening regions.

    SPACER PROCESS FOR ON PITCH CONTACTS AND RELATED STRUCTURES
    6.
    发明申请
    SPACER PROCESS FOR ON PITCH CONTACTS AND RELATED STRUCTURES 审中-公开
    用于触点接触和相关结构的间隔工艺

    公开(公告)号：US20140299997A1

    公开(公告)日：2014-10-09

    申请号：US14311696

    申请日：2014-06-23

    Applicant: Micron Technology, Inc.

    Inventor： Gurtej Sandhu ,  Mark Kiehlbauch ,  Steve Kramer ,  John Smythe

    IPC: H01L21/768 ,  H01L23/528

    CPC classification number: H01L21/76816 ,  H01L21/0337 ,  H01L21/0338 ,  H01L23/528 ,  H01L2924/0002 ,  Y10S438/942 ,  H01L2924/00

    Abstract: Methods are disclosed, including for increasing the density of isolated features in an integrated circuit. Also disclosed are associated structures. In some embodiments, contacts are formed on pitch with other structures, such as conductive interconnects that may be formed by pitch multiplication. To form the contacts, in some embodiments, a pattern corresponding to some of the contacts is formed in a selectively definable material such as photoresist. Features in the selectively definable material are trimmed, and spacer material is blanket deposited over the features and the deposited material is then etched to leave spacers on sides of the features. The selectively definable material is removed, leaving a mask defined by the spacer material. The pattern defined by the spacer material may be transferred to a substrate, to form on pitch contacts. In some embodiments, the on pitch contacts may be used to electrically contact conductive interconnects in the substrate.

    Abstract translation: 公开了包括用于增加集成电路中的隔离特征的密度的方法。 还公开了相关联的结构。 在一些实施例中，触点是与其他结构形成的，例如可以由间距倍增形成的导电互连。 为了形成触点，在一些实施例中，对应于一些触点的图案形成在诸如光致抗蚀剂的可选择定义的材料中。 在可选择定义的材料中的特征被修整，并且间隔物材料被毯子沉积在特征上，然后蚀刻沉积的材料以在特征的侧面留下间隔物。 去除可选择定义的材料，留下由间隔物材料限定的掩模。 由间隔物材料限定的图案可以转移到基底上，以形成间距接触。 在一些实施例中，上电触点可用于电接触衬底中的导电互连。

    Capacitor Forming Methods
    7.
    发明申请
    Capacitor Forming Methods 有权
    电容器形成方法

    公开(公告)号：US20140227852A1

    公开(公告)日：2014-08-14

    申请号：US14255300

    申请日：2014-04-17

    Applicant: Micron Technology, Inc.

    Inventor： Mark Kiehlbauch

    IPC: H01L49/02

    CPC classification number: H01L28/60 ,  H01G4/33 ,  H01G13/00 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/91

    Abstract: A capacitor forming method includes forming an electrically conductive support material over a substrate, forming an opening through at least the support material to the substrate, and, after forming the opening, forming a capacitor structure contacting the substrate and the support material in the opening. The support material contains at least 25 at % carbon. Another capacitor forming method includes forming a support material over a substrate, forming an opening through at least the support material to the substrate, and, after forming the opening, forming a capacitor structure contacting the substrate and the support material in the opening. The support material contains at least 20 at % carbon. The support material has a thickness and the opening has an aspect ratio 20:1 or greater within the thickness of the support material.

    Abstract translation: 电容器形成方法包括在衬底上形成导电支撑材料，通过至少所述支撑材料形成到所述衬底的开口，并且在形成所述开口之后，形成接触所述衬底和所述开口中的所述支撑材料的电容器结构。 载体材料含有至少25原子％的碳。 另一种电容器形成方法包括在衬底上形成支撑材料，通过至少支撑材料形成到衬底的开口，并且在形成开口之后，形成接触衬底和开口中的支撑材料的电容器结构。 载体材料含有至少20原子％的碳。 支撑材料具有厚度，并且开口在支撑材料的厚度内具有20:1或更大的纵横比。

    Semiconductor Constructions, and Semiconductor Processing Methods
    8.
    发明申请
    Semiconductor Constructions, and Semiconductor Processing Methods 有权
    半导体构造和半导体处理方法

    公开(公告)号：US20160005742A1

    公开(公告)日：2016-01-07

    申请号：US14848115

    申请日：2015-09-08

    Applicant: Micron Technology, Inc.

    Inventor： Mark Kiehlbauch

    IPC: H01L27/108 ,  H01L23/535 ,  H01L23/528

    CPC classification number: H01L27/10808 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823475 ,  H01L23/528 ,  H01L23/535 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Some embodiments include methods in which a pair of spaced-apart adjacent features is formed over a substrate. The features have silicon dioxide surfaces. Silicon nitride is deposited between the features. A first region of the silicon nitride is protected with a mask while a second region is not. The second region is removed to form an opening between the features. Some embodiments include semiconductor constructions that contain a pair of spaced-apart adjacent features. The features are lines extending along a first direction, and are spaced from one another by a trench. Alternating plugs and intervening materials are within the trench, with the plugs and intervening materials alternating along the first direction. The intervening materials consist of silicon nitride, and the plugs have lateral peripheries that directly contact silicon dioxide of the features, and that directly contact silicon nitride of the intervening regions.

    Abstract translation: 一些实施例包括在衬底上形成一对间隔开的相邻特征的方法。 这些特征具有二氧化硅表面。 氮化硅沉积在特征之间。 氮化硅的第一区域用掩模保护，而第二区域不被保护。 去除第二区域以在特征之间形成开口。 一些实施例包括包含一对间隔开的相邻特征的半导体构造。 特征是沿着第一方向延伸的线，并且通过沟槽彼此间隔开。 交替插头和插入材料在沟槽内，插头和插入材料沿第一方向交替。 中间材料由氮化硅组成，并且插塞具有直接接触特征的二氧化硅并且直接接触中间区域的氮化硅的侧向周边。

    Capacitor forming methods
    9.
    发明授权
    Capacitor forming methods 有权
    电容器形成方法

    公开(公告)号：US09224798B2

    公开(公告)日：2015-12-29

    申请号：US14255300

    申请日：2014-04-17

    Applicant: Micron Technology, Inc.

    Inventor： Mark Kiehlbauch

    IPC: H01L49/02 ,  H01G4/33 ,  H01L27/108 ,  H01G13/00

    CPC classification number: H01L28/60 ,  H01G4/33 ,  H01G13/00 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/91

    Abstract: A capacitor forming method includes forming an electrically conductive support material over a substrate, forming an opening through at least the support material to the substrate, and, after forming the opening, forming a capacitor structure contacting the substrate and the support material in the opening. The support material contains at least 25 at % carbon. Another capacitor forming method includes forming a support material over a substrate, forming an opening through at least the support material to the substrate, and, after forming the opening, forming a capacitor structure contacting the substrate and the support material in the opening. The support material contains at least 20 at % carbon. The support material has a thickness and the opening has an aspect ratio 20:1 or greater within the thickness of the support material.

    Abstract translation: 电容器形成方法包括在衬底上形成导电支撑材料，通过至少所述支撑材料形成到所述衬底的开口，并且在形成所述开口之后，形成接触所述衬底和所述开口中的所述支撑材料的电容器结构。 载体材料含有至少25原子％的碳。 另一种电容器形成方法包括在衬底上形成支撑材料，通过至少支撑材料形成到衬底的开口，并且在形成开口之后，形成接触衬底和开口中的支撑材料的电容器结构。 载体材料含有至少20原子％的碳。 支撑材料具有厚度，并且开口在支撑材料的厚度内具有20:1或更大的纵横比。

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