公开(公告)号：US20240071514A1

公开(公告)日：2024-02-29

申请号：US17898043

申请日：2022-08-29

Applicant: Micron Technology, Inc.

Inventor： Christina PAPAGIANNI ,  Murong LANG ,  Peng ZHANG ,  Zhenming ZHOU

IPC: G11C16/16 ,  G11C16/08 ,  G11C16/34

CPC classification number: G11C16/16 ,  G11C16/08 ,  G11C16/3404 ,  G11C16/3495

Abstract: A controller of a memory device may identify a plurality of word line groups, included in a block of a memory of the memory device, that include erased pages of the block. The controller may identify a subset of word line groups, of the plurality of word line groups, for a NAND detect empty page (NDEP) scan operation. The controller may perform, based on identifying the subset of word line groups, the NDEP scan operation for the subset of word line groups. A voltage threshold for the NDEP scan may be based on an offset voltage that can be adaptive based on parameters such as quantity of program-erase cycles, memory cell type, and/or operating temperature, among other examples.

公开(公告)号：US20220013185A1

公开(公告)日：2022-01-13

申请号：US16925222

申请日：2020-07-09

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Zhongguang XU ,  Murong LANG ,  Zhenming ZHOU

IPC: G11C29/10 ,  G11C29/52

Abstract: An accelerated seasoning cycle criterion is associated with a memory die of a number of memory dies. The memory die is subjected to one or more accelerated seasoning conditions during accelerated seasoning cycles. Responsive to determining that the accelerated seasoning cycle criterion has been satisfied, a defect scan is performed on the memory die. The memory die is associated with a respective reliability bin of a plurality of reliability bins in view of a result of the defect scan, wherein the result of the defect scan satisfies one or more predetermined threshold reliability criteria corresponding to the respective reliability bin.

公开(公告)号：US20240176496A1

公开(公告)日：2024-05-30

申请号：US18514926

申请日：2023-11-20

Applicant: Micron Technology, Inc.

Inventor： Zhongguang XU ,  Ronit Roneel PRAKASH ,  Murong LANG ,  Ching-Huang LU ,  Zhenming ZHOU

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0659 ,  G06F3/0679

Abstract: Methods, systems, and apparatuses include moving a portion of memory to a garbage pool in response to determining that the portion of memory is invalid. The portion of memory is erased in response to determining that the portion of memory is invalid. A request to move an additional portion of memory to a free pool from the garbage pool is received. A free pool includes a queue including erased portions of memory, which serve as next portions of memory to fulfill subsequent cursor requests. The erased portion of memory is moved from the garbage pool to the free pool.

公开(公告)号：US20240071506A1

公开(公告)日：2024-02-29

申请号：US17823191

申请日：2022-08-30

Applicant: Micron Technology, Inc.

Inventor： Zhongguang XU ,  Murong LANG ,  Zhenming ZHOU ,  Ugo RUSSO ,  Niccolo' RIGHETTI ,  Nicola CIOCCHINI

IPC: G11C16/10 ,  G11C16/08 ,  G11C16/16 ,  G11C16/28

CPC classification number: G11C16/102 ,  G11C16/08 ,  G11C16/16 ,  G11C16/28

Abstract: A memory device may include a memory and a controller. The controller may be configured to receive a read command associated with a block of the memory. The controller may be configured to determine a block type associated with the block. The controller may be configured to identify, based on the block type, one or more read voltage offsets for a read operation associated with the block. The controller may be configured to perform the read operation based on the one or more read voltage offsets.

公开(公告)号：US20240170090A1

公开(公告)日：2024-05-23

申请号：US18492252

申请日：2023-10-23

Applicant: Micron Technology, Inc.

Inventor： Peng ZHANG ,  Lei LIN ,  Zhongguang XU ,  Li-Te CHANG ,  Zhengang CHEN ,  Murong LANG ,  Zhenming ZHOU

IPC: G11C29/52 ,  G11C16/10 ,  G11C16/26

CPC classification number: G11C29/52 ,  G11C16/102 ,  G11C16/26

Abstract: In some implementations, a memory device may determine that a power loss has occurred. The memory device may determine a last written page (LWP) location associated with an LWP of a block of a memory of the memory device. The memory device may determine one of: a word line group (WLG) associated with the LWP location and at least one WLG-dependent offset associated with the WLG, or a partial block (PB) fill ratio associated with the LWP location and at least one PB-fill-ratio-dependent offset associated with the PB fill ratio. The memory device may perform a power loss error detection procedure based on one of the at least one WLG-dependent offset or the at least one PB-fill-ratio offset by applying the one of the at least one WLG-dependent offset or the at least one PB-fill-ratio offset to at least one read reference voltage.

公开(公告)号：US20230043091A1

公开(公告)日：2023-02-09

申请号：US17393020

申请日：2021-08-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Li-Te CHANG ,  Murong LANG ,  Zhongguang XU ,  Zhenming ZHOU

IPC: G11C11/406 ,  G11C11/4074 ,  G11C11/4096

Abstract: A processing device of a memory sub-system is configured to determine a current refresh frequency associated with the memory device, the current refresh frequency specifying a rate of performing refresh operations on data stored at the memory device; compute an updated refresh frequency by updating the current refresh frequency based on a criterion reflecting a result of comparing one or more operating parameters of the memory device to their respective threshold values; and perform a refresh operation on data stored at the memory device according to the updated refresh frequency.

公开(公告)号：US20220012121A1

公开(公告)日：2022-01-13

申请号：US16925215

申请日：2020-07-09

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Zhongguang XU ,  Murong LANG ,  Zhenming ZHOU

IPC: G06F11/10 ,  G11C29/00 ,  G11C16/10

Abstract: An initial level of sensing voltage is set based on one or more characteristics of the segment of the memory device. A count for operational cycles for a segment of a memory device is set. Responsive to determining that a number of operational cycles performed on the segment of the memory device has reached the set count of operational cycles, the sensing voltage is varied with respect to the initial level of sensing voltage. The sensing voltage is adjusted to a new level based on wearing of the segment of the memory device during the number of operational cycles performed on the segment of the memory device.