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    Method and device for selecting one of multiple clock signals based on frequency differences of such clock signals
    1.
    发明授权
    Method and device for selecting one of multiple clock signals based on frequency differences of such clock signals 有权
    基于这种时钟信号的频率差选择多个时钟信号之一的方法和装置

    公开(公告)号：US07343510B1

    公开(公告)日：2008-03-11

    申请号：US11019731

    申请日：2004-12-21

    申请人： Mark Ross ,  S. Babar Raza ,  Dimitris Pantelakis ,  Anup Nayak ,  Walter Bridgewater

    发明人： Mark Ross ,  S. Babar Raza ,  Dimitris Pantelakis ,  Anup Nayak ,  Walter Bridgewater

    IPC分类号： G06F1/12

    CPC分类号： G06F1/04

    摘要： A clock detection and selection circuit (100) can include a first counter (102-0) that generates a first count value CNT1 according to a first clock signal CLK1 and a second counter (102-1) that generates a second count value CNT2 according to a second clock signal CLK2. First separation-detect logic (102-0) and second separation-detect logic (102-1) determine if a pre-specified difference exists between a first count value (CNT1/CNT1′) and second count value (CNT2/CNT2′). According to such determinations, separation information (INF—1 and INF—2) can be generated indicating which clock signal (CLK1 or CLK2) is faster. Selection logic (106) can select a faster of the clock signals (CLK1 or CLK2) if the separation information values confirm one another.

    摘要翻译： 时钟检测和选择电路（100）可以包括根据第一时钟信号CLK 1产生第一计数值CNT 1的第一计数器（102-0）和产生第二计数值的第二计数器（102-1） CNT 2根据第二时钟信号CLK 2。 第一分离检测逻辑（102-0）和第二分离检测逻辑（102-1）确定在第一计数值（CNT 1 / CNT 1'）和第二计数值（CNT 2 / CNT 2'）。 根据这样的确定，可以产生指示哪个时钟信号（CLK 1或CLK 2）更快的分离信息（INF＆gt; 1＆lt; 1＆gt; 1和INF＆gt; 2）。 如果分离信息值彼此确认，则选择逻辑（106）可选择更快的时钟信号（CLK 1或CLK 2）。

    System and method for staging concurrent accesses to a memory address location via a single port using a high speed sampling clock
    2.
    发明授权
    System and method for staging concurrent accesses to a memory address location via a single port using a high speed sampling clock 有权
    用于通过使用高速采样时钟的单个端口对存储器地址位置进行并发访问的系统和方法

    公开(公告)号：US07184359B1

    公开(公告)日：2007-02-27

    申请号：US11003292

    申请日：2004-12-03

    申请人： Walter F. Bridgewater ,  Anup Nayak ,  Dimitris C. Pantelakis ,  S. Babar Raza

    发明人： Walter F. Bridgewater ,  Anup Nayak ,  Dimitris C. Pantelakis ,  S. Babar Raza

    IPC分类号： G11C8/00

    CPC分类号： G11C11/412 ,  G11C8/16 ,  G11C11/418

    摘要： A memory device, apparatus and method are provided for accessing memory cells. The device, apparatus, and method allow two or more electronic subsystems with corresponding external ports to access a single array of memory elements via a single internal port. Address, data, and control signals from each of the external ports are multiplexed onto the word line drivers and de-multiplexed from the sense amplifiers. Multiplexing and de-multiplexing operations are sequenced based on a state machine that receives synchronized signals from the external port. The synchronized signal can be clock signals that are synchronized to a high-speed sampling clock. Synchronization and sequencing functions can occur over a relatively few number of cycles of the high-speed sampling clock to minimize the time for resolving access conflicts, thereby maximizing the number of external ports which can access the internal port of the array.

    摘要翻译： 提供存储器件，装置和方法来访问存储器单元。 设备，装置和方法允许具有相应外部端口的两个或多个电子子系统通过单个内部端口访问单个存储器单元阵列。 来自每个外部端口的地址，数据和控制信号被复用到字线驱动器上，并从读出放大器解复用。 基于从外部端口接收同步信号的状态机对多路复用和解复用操作进行排序。 同步信号可以是与高速采样时钟同步的时钟信号。 同步和排序功能可以在高速采样时钟的相对较少数量的周期内发生，以最小化解决访问冲突的时间，从而最大化可以访问阵列的内部端口的外部端口的数量。

    FIFO read interface protocol
    3.
    发明授权
    FIFO read interface protocol 有权
    FIFO读接口协议

    公开(公告)号：US06810098B1

    公开(公告)日：2004-10-26

    申请号：US09732686

    申请日：2000-12-08

    申请人： Somnath Paul ,  S. Babar Raza

    发明人： Somnath Paul ,  S. Babar Raza

    IPC分类号： H04L700

    CPC分类号： G06F5/065

    摘要： An apparatus configured to interface a first clock speed of a multiqueue storage device and a second clock speed of an interface. The apparatus may be configured to control a flow of variable size data packets.

    摘要翻译： 一种被配置为将多队列存储设备的第一时钟速度和接口的第二时钟速度进行接口的设备。 该装置可以被配置为控制可变大小数据分组的流。

    Circuit and method for supporting multicast/broadcast operations in multi-queue storage devices
    4.
    发明授权
    Circuit and method for supporting multicast/broadcast operations in multi-queue storage devices 有权
    在多队列存储设备中支持多播/广播操作的电路和方法

    公开(公告)号：US06584517B1

    公开(公告)日：2003-06-24

    申请号：US09347046

    申请日：1999-07-02

    申请人： S. Babar Raza

    发明人： S. Babar Raza

    IPC分类号： G06F300

    CPC分类号： H04L49/90

    摘要： A circuit comprising a memory and a control circuit. The memory may be configured to (i) hold one or more packets of information and (ii) send the held packets of information in response to one or more control signals. The control circuit may be configured to generate the one or more control signals.

    摘要翻译： 一种包括存储器和控制电路的电路。 存储器可以被配置为（i）保持一个或多个信息分组，并且（ii）响应于一个或多个控制信号发送所保持的信息分组。 控制电路可以被配置为产生一个或多个控制信号。

    Method and architecture for synchronizing a transport and path overhead generator and/or extractor to an path overhead transport and path processor
    5.
    发明授权
    Method and architecture for synchronizing a transport and path overhead generator and/or extractor to an path overhead transport and path processor 有权
    将传输和路径开销生成器和/或提取器同步到路径开销传输和路径处理器的方法和架构

    公开(公告)号：US06502197B1

    公开(公告)日：2002-12-31

    申请号：US09436314

    申请日：1999-11-08

    申请人： S. Babar Raza

    发明人： S. Babar Raza

    IPC分类号： G06F112

    CPC分类号： H04J3/0685 ,  H04J3/0623 ,  H04J2203/0025

    摘要： An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to synchronize at least one transport overhead byte with a pulse on an external pin. The second circuit may be configured to synchronize the transport overhead byte to the overhead processor. The overhead processor may be synchronized with (i) an overhead generator and (ii) an overhead extractor.

    摘要翻译： 一种包括第一电路和第二电路的装置。 第一电路可以被配置为使至少一个传输开销字节与外部引脚上的脉冲同步。 第二电路可以被配置为将传输开销字节同步到架空处理器。 开销处理器可以与（i）架空发生器和（ii）开销提取器同步。

    Method and apparatus to generate mask programmable device
    6.
    发明授权
    Method and apparatus to generate mask programmable device 有权
    生成掩模可编程器件的方法和装置

    公开(公告)号：US6118299A

    公开(公告)日：2000-09-12

    申请号：US324375

    申请日：1999-06-02

    申请人： S. Babar Raza

    发明人： S. Babar Raza

    IPC分类号： H03K19/173 ,  G06F7/38

    CPC分类号： H03K19/1735

    摘要： The present invention concerns a mask-programmed cell comprising an input, an output and a transistor. The transistor has a first terminal and a second terminal. The cell may be configured in a first of three possible states when (a) the cell input is coupled to the first terminal via a first of two mask-programmed interconnects, and (b) the second terminal is coupled to the output. The cell may be configured in a second of three possible states when (a) a complement of the cell input is coupled to the first terminal via a second of the two mask-programmed interconnects, and (b) the second terminal is coupled to the output. The cell may be configured in a third of the three possible states when either the second terminal or the output is coupled to a predetermined level signal.

    摘要翻译： 本发明涉及包括输入，输出和晶体管的掩模编程单元。 晶体管具有第一端子和第二端子。 当（a）单元输入经由两个屏蔽编程的互连中的第一个耦合到第一终端，并且（b）第二端耦合到输出时，单元可以被配置为三种可能状态中的第一种状态。 当（a）单元输入的补码经由两个屏蔽编程的互连中的第二个耦合到第一终端时，单元可以被配置为三种可能状态中的第二种状态，并且（b）第二端耦合到 输出。 当第二端子或输出端耦合到预定电平信号时，单元可以被配置为三种可能状态的三分之一。

    Method and apparatus to generate mask programmable device
    7.
    发明授权
    Method and apparatus to generate mask programmable device 失效
    生成掩模可编程器件的方法和装置

    公开(公告)号：US5943488A

    公开(公告)日：1999-08-24

    申请号：US669713

    申请日：1996-06-26

    申请人： S. Babar Raza

    发明人： S. Babar Raza

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5045

    摘要： A mask-programmable and mask-programmed interconnect matrix is disclosed in which at least one of a plurality of output conductors may be interconnected via a mask-programmed interconnection to at least one input conductor. Also disclosed is a method of creating a mask programmed device implementing a logic function comprising the steps of creating a field-programmable device or array and a mask-programmable device or array, determining an interconnect map that would implement the logic function on the field programmable device or array, and implementing the interconnect map on the mask programmable device or array by mask programming the interconnects determined in the interconnect map onto the mask programmable device or array. Also disclosed is a method of generating a programmed device, the method comprising the steps of producing a base programmable mask, producing a layout table, determining a logic function to be implemented on the programmed device, generating a programmed mask based on the base programmable mask, the layout table, and the logic function, and implementing the programmed mask.

    摘要翻译： 公开了一种掩模可编程和掩模编程的互连矩阵，其中多个输出导体中的至少一个可经由掩模编程的互连互连至至少一个输入导体。 还公开了一种创建实现逻辑功能的掩模编程设备的方法，该逻辑功能包括以下步骤：创建现场可编程设备或阵列和掩模可编程设备或阵列，确定将实现现场可编程的逻辑功能的互连图 设备或阵列，以及通过将在互连图中确定的互连掩模编程到掩模可编程设备或阵列上来在掩模可编程设备或阵列上实现互连图。 还公开了一种生成编程设备的方法，该方法包括以下步骤：产生基本可编程掩模，产生布局表，确定要在编程设备上实现的逻辑功能，基于基本可编程掩码生成编程掩码 ，布局表和逻辑功能，并实现编程的掩码。

    Methods for maximizing routability in a programmable interconnect matrix having less than full connectability
    8.
    发明授权
    Methods for maximizing routability in a programmable interconnect matrix having less than full connectability 失效
    在具有小于完全可连接性的可编程互连矩阵中最大化可路由性的方法

    公开(公告)号：US5689686A

    公开(公告)日：1997-11-18

    申请号：US822769

    申请日：1997-03-21

    申请人： Hagop A. Nazarian ,  Stephen M. Douglass ,  W. Alfred Graf ,  S. Babar Raza ,  Sundar Rajan ,  Shiva Sorooshian Borzin ,  Darren Neuman

    发明人： Hagop A. Nazarian ,  Stephen M. Douglass ,  W. Alfred Graf ,  S. Babar Raza ,  Sundar Rajan ,  Shiva Sorooshian Borzin ,  Darren Neuman

    IPC分类号： H04Q3/545 ,  H04Q3/68 ,  H04Q11/04 ,  H04Q3/04

    CPC分类号： H04Q11/0407 ,  H04Q11/04 ,  H04Q3/545 ,  H04Q3/68 ,  H04Q2213/1302 ,  H04Q2213/1304 ,  H04Q2213/1305 ,  H04Q2213/13141 ,  H04Q2213/13204 ,  H04Q2213/13213 ,  H04Q2213/13305 ,  H04Q2213/1332 ,  H04Q2213/1334 ,  Y10T307/74 ,  Y10T307/76

    摘要： Methods for designing a programmable interconnect matrix having reduced connectivity to achieve maximum routability for the reduced connectivity. An array of multiplexors, each having a multiplexor width w.sub.mux that is less than number of input conductors for the programmable matrix, are coupled to the input conductors of the programmable interconnect matrix such that the number of input signals shared between any two multiplexors is less than the multiplexor width w.sub.mux and such that each input signal has approximately the same number of chances to route. To better ensure the successful routing of input signals by a programmable interconnect matrix designed according to the present methods, improved routing methods are also described. According to a first embodiment, routing is accomplished by swapping successfully routed input signals with a blocked input signal and determining whether the input signal that has been swapped out may be routed through available multiplexors. According to a second embodiment, a predictive swapping technique is used whereby successfully routed signals qualified to provide a blocked signal with a route are first checked to determine whether a successful routing will be provided before swapping in the blocked output signal.

    摘要翻译： 用于设计具有降低的连接性以实现降低的连接性的最大可路由性的可编程互连矩阵的方法。 每个具有小于可编程矩阵的输入导体数量的多路复用器宽度wmux的多路复用器阵列耦合到可编程互连矩阵的输入导体，使得任何两个多路复用器之间共享的输入信号的数量小于 多路复用器宽度wmux，并且使得每个输入信号具有大致相同数量的路由机会。 为了更好地确保通过根据本方法设计的可编程互连矩阵成功地路由输入信号，还描述了改进的路由方法。 根据第一实施例，通过用阻塞的输入信号交换成功路由的输入信号并且确定是否已被换出的输入信号可以通过可用的多路复用器被路由来实现路由。 根据第二实施例，使用预测交换技术，由此首先检查合格以提供具有路由的阻塞信号的成功路由信号，以确定在交换阻塞的输出信号之前是否提供成功的路由。