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    Optically transparent, scratch-resistant, diamond-like carbon coatings
    2.
    发明授权
    Optically transparent, scratch-resistant, diamond-like carbon coatings 失效
    光学透明，耐刮擦，类金刚石碳涂层

    公开(公告)号：US06572935B1

    公开(公告)日：2003-06-03

    申请号：US09428269

    申请日：1999-10-27

    申请人： Xiao-Ming He ,  Deok-Hyung Lee ,  Michael A. Nastasi ,  Kevin C. Walter ,  Michel G. Tuszewski

    发明人： Xiao-Ming He ,  Deok-Hyung Lee ,  Michael A. Nastasi ,  Kevin C. Walter ,  Michel G. Tuszewski

    IPC分类号： C23C1627

    CPC分类号： C23C16/26 ,  H01J37/32412 ,  Y10S427/103 ,  Y10S427/104

    摘要： A plasma-based method for the deposition of diamond-like carbon (DLC) coatings is described. The process uses a radio-frequency inductively coupled discharge to generate a plasma at relatively low gas pressures. The deposition process is environmentally friendly and scaleable to large areas, and components that have geometrically complicated surfaces can be processed. The method has been used to deposit adherent 100-400 nm thick DLC coatings on metals, glass, and polymers. These coatings are between three and four times harder than steel and are therefore scratch resistant, and transparent to visible light. Boron and silicon doping of the DLC coatings have produced coatings having improved optical properties and lower coating stress levels, but with slightly lower hardness.

    摘要翻译： 描述了用于沉积类金刚石（DLC）涂层的基于等离子体的方法。 该过程使用射频感应耦合放电在相对低的气体压力下产生等离子体。 沉积工艺对于大面积的环境友好和可扩展，并且可以处理具有几何复杂表面的部件。 该方法已用于在金属，玻璃和聚合物上沉积100-400nm厚的DLC涂层。 这些涂层比钢硬三至四倍，因此具有耐划伤性，对可见光透明。 DLC涂层的硼和硅掺杂已经产生具有改善的光学性能和较低涂层应力水平但具有稍低的硬度的涂层。

    Methods of fabricating MOS transistors having recesses with elevated source/drain regions
    3.
    发明授权
    Methods of fabricating MOS transistors having recesses with elevated source/drain regions 有权
    制造具有升高的源极/漏极区域的凹槽的MOS晶体管的方法

    公开(公告)号：US08039350B2

    公开(公告)日：2011-10-18

    申请号：US12582073

    申请日：2009-10-20

    申请人： Yong-Hoon Son ,  Si-Young Choi ,  Byeong-Chan Lee ,  Deok-Hyung Lee ,  In-Soo Jung

    发明人： Yong-Hoon Son ,  Si-Young Choi ,  Byeong-Chan Lee ,  Deok-Hyung Lee ,  In-Soo Jung

    IPC分类号： H01L21/336

    CPC分类号： H01L29/6659 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7833

    摘要： Methods of fabricating metal-oxide-semiconductor (MOS) transistors having elevated source/drain regions are provided. The MOS transistors formed by these methods may include a gate pattern formed to cross over a predetermined region of a substrate. Recessed regions are provided in the substrate adjacent to the gate pattern. Epitaxial layers are provided on bottom surfaces of the recessed regions. High concentration impurity regions are provided in the epitaxial layers. The recessed regions may be formed using a chemical dry etching techniques.

    摘要翻译： 提供了具有升高的源极/漏极区域的金属氧化物半导体（MOS）晶体管的制造方法。 通过这些方法形成的MOS晶体管可以包括形成为跨越衬底的预定区域的栅极图案。 凹陷区域设置在与栅极图案相邻的衬底中。 外凹层设置在凹陷区域的底表面上。 在外延层中设置高浓度杂质区。 凹陷区域可以使用化学干蚀刻技术形成。

    Fin field effect transistors with low resistance contact structures
    5.
    发明授权
    Fin field effect transistors with low resistance contact structures 有权
    具有低电阻接触结构的Fin场效应晶体管

    公开(公告)号：US07385237B2

    公开(公告)日：2008-06-10

    申请号：US11076185

    申请日：2005-03-09

    申请人： Deok-Hyung Lee ,  In-Deog Bae ,  Byeong-Chan Lee ,  Jong-Wook Lee

    发明人： Deok-Hyung Lee ,  In-Deog Bae ,  Byeong-Chan Lee ,  Jong-Wook Lee

    IPC分类号： H01L29/08

    CPC分类号： H01L29/7851 ,  H01L29/66795

    摘要： Fin FET semiconductor devices are provided which include a substrate, an active pattern that protrudes vertically from the substrate and that extends laterally in a first direction, a device isolation layer which has a top surface that is lower than a top surface of the active pattern, a gate structure on the substrate that extends laterally in a second direction to cover a portion of the active pattern and a conductive layer that is on at least portions of side surfaces of the active pattern that are adjacent a side portion of the gate structure. The conductive layer may comprise a semiconductor layer, and the semiconductor layer may be in electrical contact with a contact pad. In other embodiments, the conductive layer may comprise a contact pad.

    摘要翻译： 提供鳍式FET半导体器件，其包括衬底，从衬底垂直突出并且在第一方向上横向延伸的有源图案，具有比活动图案的顶表面低的顶表面的器件隔离层， 基板上的栅极结构，其在第二方向上横向延伸以覆盖有源图案的一部分，以及位于与栅极结构的侧部相邻的有源图案的至少部分侧表面上的导电层。 导电层可以包括半导体层，并且半导体层可以与接触焊盘电接触。 在其它实施例中，导电层可以包括接触垫。

    FIN FIELD EFFECT TRANSISTOR AND METHOD OF MANUFACTURING THE SAME
    6.
    发明申请
    FIN FIELD EFFECT TRANSISTOR AND METHOD OF MANUFACTURING THE SAME 有权
    FIN场效应晶体管及其制造方法

    公开(公告)号：US20080093674A1

    公开(公告)日：2008-04-24

    申请号：US11952676

    申请日：2007-12-07

    申请人： Deok-Hyung Lee ,  Yu-Gyun Shin ,  Jong-Wook Lee ,  Min-Gu Kang

    发明人： Deok-Hyung Lee ,  Yu-Gyun Shin ,  Jong-Wook Lee ,  Min-Gu Kang

    IPC分类号： H01L29/78

    CPC分类号： H01L29/7851 ,  H01L29/66795 ,  H01L29/7854

    摘要： In a fin field effect transistor (FET), an active pattern protrudes in a vertical direction from a substrate and extends across the substrate in a first horizontal direction. A first silicon nitride pattern is formed on the active pattern, and a first oxide pattern and a second silicon nitride pattern are sequentially formed on the substrate and on a sidewall of a lower portion of the active pattern. A device isolation layer is formed on the second silicon nitride pattern, and a top surface of the device isolation layer is coplanar with top surfaces of the oxide pattern and the second silicon nitride pattern. A buffer pattern having an etching selectivity with respect to the second silicon nitride pattern is formed between the first oxide pattern and the second silicon nitride pattern. Internal stresses that can be generated in sidewalls of the active pattern are sufficiently released and an original shape of the first silicon nitride pattern remains unchanged, thereby improving electrical characteristics of the fin FET.

    摘要翻译： 在鳍状场效应晶体管（FET）中，有源图案在垂直方向上从基板突出，并且在第一水平方向上延伸穿过基板。 第一氮化硅图案形成在有源图案上，并且第一氧化物图案和第二氮化硅图案依次形成在衬底上和活性图案的下部的侧壁上。 在第二氮化硅图案上形成器件隔离层，器件隔离层的顶表面与氧化物图案和第二氮化硅图案的顶表面共面。 在第一氧化物图案和第二氮化硅图案之间形成具有相对于第二氮化硅图案的蚀刻选择性的缓冲图案。 可以在有源图案的侧壁中产生的内部应力被充分地释放，并且第一氮化硅图案的原始形状保持不变，从而改善了鳍式FET的电特性。

    Fin-field effect transistors (Fin-FETs) having protection layers
    7.
    发明申请
    Fin-field effect transistors (Fin-FETs) having protection layers 有权
    具有保护层的鳍场效应晶体管（Fin-FET）

    公开(公告)号：US20070034925A1

    公开(公告)日：2007-02-15

    申请号：US11586225

    申请日：2006-10-25

    申请人： Deok-Hyung Lee ,  Si-Young Choi ,  Byeong-Chan Lee ,  In-Soo Jung ,  Jin-Hwa Heo

    发明人： Deok-Hyung Lee ,  Si-Young Choi ,  Byeong-Chan Lee ,  In-Soo Jung ,  Jin-Hwa Heo

    IPC分类号： H01L29/94

    CPC分类号： H01L29/7851 ,  H01L29/66795

    摘要： Fin-Field Effect Transistors (Fin-FETs) are provided. A fin is provided on an integrated circuit substrate. The fin defines a trench on the integrated circuit substrate. A first insulation layer is provided in the trench such that a surface of the first insulation layer is recessed beneath a surface of the fin exposing sidewalls of the fin. A protection layer is provided on the first insulation layer and a second insulation layer is provided on the protection layer in the trench such that protection layer is between the second insulation layer and the sidewalls of the fin.

    摘要翻译： 提供了场效应晶体管（Fin-FET）。 翅片设置在集成电路基板上。 翅片限定集成电路基板上的沟槽。 第一绝缘层设置在沟槽中，使得第一绝缘层的表面在鳍片的暴露翅片侧壁的表面下方凹进。 保护层设置在第一绝缘层上，第二绝缘层设置在沟槽中的保护层上，使得保护层位于第二绝缘层和鳍的侧壁之间。

    Methods for fabricating fin field effect transistors using a protective layer to reduce etching damage
    8.
    发明授权
    Methods for fabricating fin field effect transistors using a protective layer to reduce etching damage 失效
    使用保护层制造鳍状场效应晶体管以减少蚀刻损伤的方法

    公开(公告)号：US07074662B2

    公开(公告)日：2006-07-11

    申请号：US10869764

    申请日：2004-06-16

    申请人： Deok-Hyung Lee ,  Si-Young Choi ,  Byeong-Chan Lee ,  Yong-Hoon Son ,  In-Soo Jung

    发明人： Deok-Hyung Lee ,  Si-Young Choi ,  Byeong-Chan Lee ,  Yong-Hoon Son ,  In-Soo Jung

    IPC分类号： H01L21/8238

    CPC分类号： H01L29/7851 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/42384 ,  H01L29/66545 ,  H01L29/66795

    摘要： A method of forming a fin field effect transistor on a semiconductor substrate includes forming a vertical fin protruding from the substrate. A buffer oxide liner is formed on a top surface and on sidewalls of the fin. A trench is then formed on the substrate, where at least a portion of the fin protrudes from a bottom surface of the trench. The trench may be formed by forming a dummy gate on at least a portion of the fin, forming an insulation layer on the fin surrounding the dummy gate, and then removing the dummy gate to expose the at least a portion of the fin, such that the trench is surrounded by the insulation layer. The buffer oxide liner is then removed from the protruding portion of the fin, and a gate is formed in the trench on the protruding portion of the fin.

    摘要翻译： 在半导体衬底上形成鳍状场效应晶体管的方法包括形成从衬底突出的垂直翅片。 缓冲氧化物衬垫形成在翅片的顶表面和侧壁上。 然后在衬底上形成沟槽，其中鳍的至少一部分从沟槽的底表面突出。 可以通过在鳍片的至少一部分上形成伪栅极来形成沟槽，在围绕虚拟栅极的鳍片上形成绝缘层，然后去除伪栅极以暴露鳍片的至少一部分，使得 沟槽被绝缘层包围。 然后从鳍片的突出部分去除缓冲氧化物衬垫，并且在鳍片的突出部分上的沟槽中形成栅极。

    Semiconductor devices having polysilicon gate layer patterns and methods of manufacturing the same
    9.
    发明授权
    Semiconductor devices having polysilicon gate layer patterns and methods of manufacturing the same 有权
    具有多晶硅栅极层图案的半导体器件及其制造方法

    公开(公告)号：US08319260B2

    公开(公告)日：2012-11-27

    申请号：US12805400

    申请日：2010-07-29

    申请人： Deok-Hyung Lee ,  Soo-Jin Hong ,  Seong-Hoon Jeong

    发明人： Deok-Hyung Lee ,  Soo-Jin Hong ,  Seong-Hoon Jeong

    IPC分类号： H01L21/336

    CPC分类号： H01L21/823807 ,  H01L21/823842 ,  H01L29/7845

    摘要： In semiconductor devices, methods of forming the same, the semiconductor device include a first gate structure having a first gate oxide layer pattern, a first polysilicon layer pattern containing atoms larger than silicon and a first hard mask layer pattern on substrates under tensile stress. N-type impurity regions are formed under the surface of the substrate on both sides of the first gate structure. A second gate structure having a second gate oxide layer pattern, a second polysilicon layer pattern containing atoms smaller than silicon and a second hard mask layer pattern on substrates under compressive stress. Additionally, P-type impurity regions are formed under the surface of the substrate on both sides of the second gate structure. The semiconductor devices have good device properties.

    摘要翻译： 在半导体器件中，形成半导体器件的方法包括具有第一栅极氧化层图案的第一栅极结构，包含比硅大的原子的第一多晶硅层图案和在拉伸应力下的基板上的第一硬掩模层图案。 在第一栅极结构的两侧的衬底的表面下方形成N型杂质区。 具有第二栅极氧化物层图案的第二栅极结构，在压缩应力下在基底上含有小于硅的原子的第二多晶硅层图案和第二硬掩模层图案。 此外，在第二栅极结构的两侧在基板的表面下方形成P型杂质区。 半导体器件具有良好的器件特性。

    Methods of fabricating MOS transistors having recesses with elevated source/drain regions
    10.
    发明授权
    Methods of fabricating MOS transistors having recesses with elevated source/drain regions 有权
    制造具有升高的源极/漏极区域的凹槽的MOS晶体管的方法

    公开(公告)号：US08304318B2

    公开(公告)日：2012-11-06

    申请号：US13241311

    申请日：2011-09-23

    申请人： Yong-Hoon Son ,  Si-Young Choi ,  Byeong-Chan Lee ,  Deok-Hyung Lee ,  In-Soo Jung

    发明人： Yong-Hoon Son ,  Si-Young Choi ,  Byeong-Chan Lee ,  Deok-Hyung Lee ,  In-Soo Jung

    IPC分类号： H01L21/336

    CPC分类号： H01L29/6659 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7833

    摘要： Methods of fabricating metal-oxide-semiconductor (MOS) transistors having elevated source/drain regions are provided. The MOS transistors formed by these methods may include a gate pattern formed to cross over a predetermined region of a substrate. Recessed regions are provided in the substrate adjacent to the gate pattern. Epitaxial layers are provided on bottom surfaces of the recessed regions. High concentration impurity regions are provided in the epitaxial layers. The recessed regions may be formed using a chemical dry etching techniques.

    摘要翻译： 提供了具有升高的源极/漏极区域的金属氧化物半导体（MOS）晶体管的制造方法。 通过这些方法形成的MOS晶体管可以包括形成为跨越衬底的预定区域的栅极图案。 凹陷区域设置在与栅极图案相邻的衬底中。 外凹层设置在凹陷区域的底表面上。 在外延层中设置高浓度杂质区。 凹陷区域可以使用化学干蚀刻技术形成。