公开(公告)号：US08692372B2

公开(公告)日：2014-04-08

申请号：US12728396

申请日：2010-03-22

Applicant: Dong-kak Lee ,  Sung-gil Kim ,  Soo-jin Hong ,  Sun-ghil Lee ,  Deok-hyung Lee

Inventor： Dong-kak Lee ,  Sung-gil Kim ,  Soo-jin Hong ,  Sun-ghil Lee ,  Deok-hyung Lee

IPC: H01L27/108 ,  H01L23/48 ,  H01L29/78

CPC classification number: H01L21/76843 ,  H01L21/28525 ,  H01L21/76847 ,  H01L21/76877 ,  H01L23/485 ,  H01L27/10855 ,  H01L27/10888 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are semiconductor devices including a semiconductor substrate, an insulating layer including a contact hole through which the semiconductor substrate is exposed, and a polysilicon layer filling the contact hole. The polysilicon layer is doped with impurities and includes an impurity-diffusion prevention layer. In the semiconductor devices, the impurities included in the polysilicon layer do not diffuse into the insulating layer and the semiconductor substrate due to the impurity-diffusion prevention layers.

Abstract translation: 提供了包括半导体衬底，包括暴露半导体衬底的接触孔的绝缘层和填充接触孔的多晶硅层的半导体器件。 多晶硅层掺杂有杂质，并且包括杂质扩散防止层。 在半导体器件中，包含在多晶硅层中的杂质不会由于杂质扩散层而扩散到绝缘层和半导体衬底中。

公开(公告)号：US07785985B2

公开(公告)日：2010-08-31

申请号：US12133772

申请日：2008-06-05

Applicant: Dong-woon Shin ,  Tai-su Park ,  Si-young Choi ,  Soo-jin Hong ,  Mi-jin Kim

Inventor： Dong-woon Shin ,  Tai-su Park ,  Si-young Choi ,  Soo-jin Hong ,  Mi-jin Kim

IPC: H01L21/76

CPC classification number: H01L21/823481 ,  H01L21/76229 ,  H01L21/823456 ,  H01L27/0921 ,  H01L27/105

Abstract: Methods of manufacturing a semiconductor device, which can reduce hot electron induced punchthrough (HEIP) and/or improve the operating characteristics of the device include selectively forming an oxynitride layer in a device isolation layer according to the characteristics of transistors isolated by the device isolation layer. The methods include forming first trenches and second trenches on a substrate, forming an oxide layer on the surfaces of the first trenches and the second trenches, selectively forming an oxynitride layer on the second trenches by using plasma ion immersion implantation (PIII), and forming a buried insulating layer in the first trenches and the second trenches. The buried insulating layer may be planarized to form a first device isolation layer in the first trenches and a second device isolation layer in the second trenches.

Abstract translation: 可以减少热电子穿透（HEIP）和/或改善器件的工作特性的半导体器件的制造方法包括根据器件隔离层隔离的晶体管的特性选择性地在器件隔离层中形成氧氮化物层 。 所述方法包括在衬底上形成第一沟槽和第二沟槽，在第一沟槽和第二沟槽的表面上形成氧化物层，通过使用等离子体离子浸没注入（PIII）在第二沟槽上选择性地形成氧氮化物层，并形成 在第一沟槽和第二沟槽中的掩埋绝缘层。 掩埋绝缘层可以被平坦化以在第一沟槽中形成第一器件隔离层，在第二沟槽中形成第二器件隔离层。

公开(公告)号：US20090311846A1

公开(公告)日：2009-12-17

申请号：US12466178

申请日：2009-05-14

Applicant: Dong-Woon Shin ,  Soo-jin Hong ,  Guk-hyon Yon ,  Si-young Choi ,  Sun-ghil Lee

Inventor： Dong-Woon Shin ,  Soo-jin Hong ,  Guk-hyon Yon ,  Si-young Choi ,  Sun-ghil Lee

IPC: H01L21/762

CPC classification number: H01L21/76229 ,  H01L21/823878 ,  H01L27/10894 ,  H01L27/11546

Abstract: A mask pattern is formed on a semiconductor substrate in which a cell region, a PMOS region, and an NMOS region are defined. Trenches are formed in the cell region, the PMOS region, and the NMOS region. A sidewall oxide layer and a protection layer are formed in the trenches, and a portion of the protection layer in the PMOS region is removed. A first device isolation insulating layer is formed on the substrate, filling the trenches. Portions of the first device isolation insulating layer are removed to expose the mask pattern and the trenches of the cell region and the NMOS region and to leave a portion of the first device isolation insulating layer in the trench in the PMOS region. A liner is formed on the portion of the first device isolation region in the trench in the PMOS region and conforming to sidewalls of the trenches in the cell region and the NMOS region. A second device isolation insulating layer is formed on the substrate, filling the trenches in the cell region and the NMOS region. Portions of the second device isolation insulating layer are removed to expose the mask pattern and to leave portions of the second device isolation insulating layer in the trenches of the cell region and the NMOS region.

Abstract translation: 在其中限定了单元区域，PMOS区域和NMOS区域的半导体衬底上形成掩模图案。 在单元区域，PMOS区域和NMOS区域中形成沟槽。 在沟槽中形成侧壁氧化物层和保护层，并且去除PMOS区域中的保护层的一部分。 在衬底上形成第一器件隔离绝缘层，填充沟槽。 去除第一器件隔离绝缘层的部分以露出掩模图案和单元区域和NMOS区域的沟槽，并且在PMOS区域的沟槽中留下第一器件隔离绝缘层的一部分。 衬垫形成在PMOS区域的沟槽中的第一器件隔离区域的部分上，并且与衬底区域和NMOS区域中的沟槽的侧壁一致。 在衬底上形成第二器件隔离绝缘层，填充单元区域和NMOS区域中的沟槽。 去除第二器件隔离绝缘层的部分以暴露掩模图案并且将第二器件隔离绝缘层的部分留在单元区域和NMOS区域的沟槽中。

公开(公告)号：US20090068823A1

公开(公告)日：2009-03-12

申请号：US12145914

申请日：2008-06-25

Applicant: Soo Jin Hong ,  Si-Young Choi ,  Tai-Su Park ,  Jin-Wook Lee ,  Jong-Hoon Kang ,  Mi-Jin Kim

Inventor： Soo Jin Hong ,  Si-Young Choi ,  Tai-Su Park ,  Jin-Wook Lee ,  Jong-Hoon Kang ,  Mi-Jin Kim

IPC: H01L21/02 ,  H01J37/08

CPC classification number: H01L21/2236 ,  H01J37/32412 ,  H01J37/32449

Abstract: In plasma ion doping operations, a wafer is positioned on a susceptor within a reaction chamber and an ion doping source gas is plasmalyzed in an upper part of the reaction chamber above a major surface of the wafer while supplying a control gas into the reaction chamber in a lower part of the reaction chamber opposite the major surface of the wafer to thereby dope ions into the major surface of the wafer. The ion doping source gas may comprise at least one halide gas, and the control gas may comprise at least one depositing gas, such as a silane gas. In further embodiments, a diluent gas, such as an inert gas, may be supplied to the reaction chamber while supplying the ion doping source gas and the control gas. Related plasma ion doping apparatus are described.

Abstract translation: 在等离子体离子掺杂操作中，将晶片定位在反应室内的基座上，并且将离子掺杂源气体在晶片的主表面上方的反应室上部进行等离子化，同时将控制气体供应到反应室中 反应室的下部与晶片的主表面相对，从而将离子掺杂到晶片的主表面。 离子掺杂源气体可以包括至少一种卤化物气体，并且控制气体可以包括至少一种沉积气体，例如硅烷气体。 在另外的实施方案中，可以向反应室供应诸如惰性气体的稀释气体，同时供应离子掺杂源气体和控制气体。 描述了相关的等离子体离子掺杂装置。

公开(公告)号：US06756654B2

公开(公告)日：2004-06-29

申请号：US10215342

申请日：2002-08-09

Applicant: Jin-Hwa Heo ,  Soo-Jin Hong

Inventor： Jin-Hwa Heo ,  Soo-Jin Hong

IPC: H01L2176

CPC classification number: H01L21/76229

Abstract: The present invention is directed toward a structure and method by which trench isolation for a wide trench and a narrow trench formed in first and second regions of a substrate may be achieved without formation of a void in an isolation layer, a groove exposing an isolation layer, or an electrical bridge between gates in a subsequent process. A lower isolation layer is formed on the substrate in a first and second trench. The lower isolation layer is patterned to fill a lower region of the first trench, and an upper isolation pattern is formed to fill the second trench and a remainder of the first trench. An aspect ratio of first trench is reduced, thereby preventing the occurrence of a void in the upper isolation layer, or a gap between the upper isolation layer and the substrate.

Abstract translation: 本发明涉及一种结构和方法，通过该结构和方法可以实现在衬底的第一和第二区域中形成的宽沟槽和窄沟槽的沟槽隔离，而不会在隔离层中形成空隙，露出隔离层 ，或在后续过程中门之间的电桥。 在第一和第二沟槽中的衬底上形成下隔离层。 图案化下部隔离层以填充第一沟槽的下部区域，并且形成上部隔离图案以填充第二沟槽和第一沟槽的其余部分。 第一沟槽的纵横比减小，从而防止在上隔离层中发生空隙或上隔离层与基板之间的间隙。

公开(公告)号：US06699799B2

公开(公告)日：2004-03-02

申请号：US10134747

申请日：2002-04-30

Applicant: Dong-Ho Ahn ,  Soo-Jin Hong ,  Jung-Il Lee ,  Kyung-won Park

Inventor： Dong-Ho Ahn ,  Soo-Jin Hong ,  Jung-Il Lee ,  Kyung-won Park

IPC: H01L21469

CPC classification number: H01L21/0234 ,  H01L21/02134 ,  H01L21/02164 ,  H01L21/02282 ,  H01L21/02348 ,  H01L21/31053 ,  H01L21/316 ,  H01L21/76229

Abstract: A method of forming a semiconductor device includes a liner is conformally stacked on a semiconductor substrate before coating an SOG layer thereon, and then curing the SOG layer, preferably in an ambient of oxygen radicals formed at a temperature of 1000° C. or higher when oxygen and hydrogen are supplied. The oxygen radicals are preferably formed by irradiating ultraviolet rays to ozone or forming oxygen plasma. The SOG layer is preferably made of a polysilazane-based material that may promote a conversion of the SOG layer into a silicon oxide layer.

Abstract translation: 一种形成半导体器件的方法包括：在涂覆SOG层之前，在半导体衬底上保形地层叠衬垫，然后固化SOG层，优选在1000℃或更高温度下形成的氧自由基的环境中固化 供应氧气和氢气。 氧自由基优选通过将紫外线照射到臭氧或形成氧等离子体来形成。 SOG层优选由可以促进SOG层转化为氧化硅层的基于聚硅氮烷的材料制成。

公开(公告)号：US06583025B2

公开(公告)日：2003-06-24

申请号：US09847280

申请日：2001-05-03

Applicant: Soo-Jin Hong

Inventor： Soo-Jin Hong

IPC: H01L212176

CPC classification number: H01L21/76224

Abstract: A method of forming a trench isolation structure prevents a nitride liner from being over-etched, i.e., prevents the so-called dent phenomenon from occurring. An etching mask pattern is formed on a semiconductor substrate. A trench is formed in the substrate by using the etching mask pattern as an etching mask. A nitride liner, serving as an oxidation barrier layer, is formed at the sides and bottom of the trench, and is then annealed in a furnace to density the same. In a subsequent etching process, such as that used to remove the etching mask pattern, the densified nitride liner resists being etched. Accordingly, a trench isolation structure having a good profile is produced.

公开(公告)号：US5677232A

公开(公告)日：1997-10-14

申请号：US754889

申请日：1996-11-22

Applicant: Sung-eui Kim ,  Soo-jin Hong

Inventor： Sung-eui Kim ,  Soo-jin Hong

IPC: H01L21/316 ,  H01L21/76 ,  H01L21/762

CPC classification number: H01L21/76202 ,  H01L21/76229 ,  H01L21/76235

Abstract: An isolation region is formed on a substrate by forming spaced apart mesas on the substrate. A first insulation region is then formed on the substrate and second insulation regions are formed on the mesas, the first insulation region being disposed between and spaced apart from a respective one of the mesas, a respective one of the second insulation regions capping a respective one of the mesas. Preferably, the first and second insulation regions are formed by forming sidewall spacers adjacent sidewall portions of the mesas and oxidizing portions of the mesas opposite the substrate and a portion of the substrate disposed between the sidewall spacers. Spaced apart trenches are formed in the substrate on opposite sides of the first insulation region, a respective one of the trenches being disposed between the first insulation region and a respective one of the mesas, preferably by removing the sidewall spacers and underlying portions of the substrate. An insulating layer is formed on the substrate, filling the trenches and covering the first insulation region, and the substrate is planarized to remove portions of the insulating layer and the second insulation regions and thereby expose underlying portions of the mesas and leave a third insulation region spanning the trenches.

Abstract translation: 通过在衬底上形成间隔开的台面，在衬底上形成隔离区。 然后在基板上形成第一绝缘区域，并且在台面上形成第二绝缘区域，第一绝缘区域设置在相应的一个台面之间并与相应的一个台面间隔开，第一绝缘区域中的相应一个覆盖相应的一个 的台面。 优选地，第一和第二绝缘区域通过形成邻近台面的侧壁部分的侧壁间隔和与衬底相对的台面的氧化部分和设置在侧壁间隔件之间的衬底的一部分而形成。 隔开的沟槽在第一绝缘区域的相对侧上的衬底中形成，相应的沟槽设置在第一绝缘区域和相应的台面之间，优选地通过去除侧壁间隔件和衬底的下面部分 。 在衬底上形成绝缘层，填充沟槽并覆盖第一绝缘区域，并且将衬底平坦化以去除绝缘层和第二绝缘区域的部分，从而暴露台面的下面部分并留下第三绝缘区域 跨越壕沟

公开(公告)号：US20110049596A1

公开(公告)日：2011-03-03

申请号：US12728396

申请日：2010-03-22

Applicant: Dong-kak Lee ,  Sung-gil Kim ,  Soo-jin Hong ,  Sun-ghil Lee ,  Deok-hyung Lee

Inventor： Dong-kak Lee ,  Sung-gil Kim ,  Soo-jin Hong ,  Sun-ghil Lee ,  Deok-hyung Lee

IPC: H01L27/108 ,  H01L23/48 ,  H01L29/78

CPC classification number: H01L21/76843 ,  H01L21/28525 ,  H01L21/76847 ,  H01L21/76877 ,  H01L23/485 ,  H01L27/10855 ,  H01L27/10888 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are semiconductor devices including a semiconductor substrate, an insulating layer including a contact hole through which the semiconductor substrate is exposed, and a polysilicon layer filling the contact hole. The polysilicon layer is doped with impurities and includes an impurity-diffusion prevention layer. In the semiconductor devices, the impurities included in the polysilicon layer do not diffuse into the insulating layer and the semiconductor substrate due to the impurity-diffusion prevention layers.

Abstract translation: 提供了包括半导体衬底，包括暴露半导体衬底的接触孔的绝缘层和填充接触孔的多晶硅层的半导体器件。 多晶硅层掺杂有杂质，并且包括杂质扩散防止层。 在半导体器件中，包含在多晶硅层中的杂质不会由于杂质扩散层而扩散到绝缘层和半导体衬底中。

公开(公告)号：US07514744B2

公开(公告)日：2009-04-07

申请号：US11322335

申请日：2005-12-30

Applicant: Gyoung-Ho Buh ,  Yu-Gyun Shin ,  Soo-Jin Hong ,  Guk-Hyon Yon

Inventor： Gyoung-Ho Buh ,  Yu-Gyun Shin ,  Soo-Jin Hong ,  Guk-Hyon Yon

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/4983 ,  H01L21/28247 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7881 ,  H01L29/792

Abstract: A semiconductor device includes a gate structure on a channel region of a semiconductor substrate adjacent to a source/drain region therein and a surface insulation layer directly on the source/drain region of the substrate adjacent to the gate structure. The device further includes a spacer on a sidewall of the gate structure adjacent to the source/drain region. A portion of the surface insulation layer adjacent the gate structure is sandwiched between the substrate and the spacer. An interface between the surface insulation layer and the source/drain region includes a plurality of interfacial states. Portions of the source/drain region immediately adjacent the interface define a carrier accumulation layer having a greater carrier concentration than other portions thereof. The carrier accumulation layer extends along the interface under the spacer. Related methods are also discussed.

Abstract translation: 半导体器件包括与半导体衬底的与源极/漏极区域相邻的沟道区域上的栅极结构，以及直接位于与栅极结构相邻的衬底的源极/漏极区域上的表面绝缘层。 该器件还包括邻近源极/漏极区的栅极结构的侧壁上的间隔物。 与栅极结构相邻的表面绝缘层的一部分夹在基板和间隔件之间。 表面绝缘层与源极/漏极区之间的界面包括多个界面状态。 紧邻界面的源极/漏极区域的部分限定了具有比其它部分更大的载流子浓度的载流子积累层。 载体积聚层沿着间隔物下的界面延伸。 还讨论了相关方法。