公开(公告)号：US07233467B2

公开(公告)日：2007-06-19

申请号：US11087384

申请日：2005-03-23

申请人： Markus Paul Josef Mergens ,  Frederic Marie Dominique De Ranter ,  Benjamin Van Camp ,  Koen Gerard Maria Verhaege ,  Phillip Czeslaw Jozwiak ,  John Armer ,  Bart Keppens

发明人： Markus Paul Josef Mergens ,  Frederic Marie Dominique De Ranter ,  Benjamin Van Camp ,  Koen Gerard Maria Verhaege ,  Phillip Czeslaw Jozwiak ,  John Armer ,  Bart Keppens

IPC分类号： H02H9/00 ,  H02H3/22 ,  H02H1/00 ,  H02H1/04 ,  H02H9/06 ,  H01C7/12

CPC分类号： H01L27/0251 ,  H03K17/08122

摘要： A method and apparatus for providing ESD event protection for a circuit using a source or bulk pump to increase the bulk and/or source potential level during an ESD event. The apparatus comprises a protection circuit that, in response to an ESD event, limits the voltage formed between two terminals of a transistor by adjusting a potential level on the second terminal.

摘要翻译： 一种用于使用源或体积泵为电路提供ESD事件保护以在ESD事件期间增加体积和/或源极电位电平的方法和装置。 该装置包括保护电路，其响应于ESD事件，通过调节第二端子上的电位电平来限制在晶体管的两个端子之间形成的电压。

公开(公告)号：US07005708B2

公开(公告)日：2006-02-28

申请号：US10435817

申请日：2003-05-12

申请人： Markus Paul Josef Mergens ,  Koen Gerard Maria Verhaege ,  Cornelius Christian Russ ,  John Armer ,  Phillip Czeslaw Jozwiak ,  Bart Keppens

发明人： Markus Paul Josef Mergens ,  Koen Gerard Maria Verhaege ,  Cornelius Christian Russ ,  John Armer ,  Phillip Czeslaw Jozwiak ,  Bart Keppens

IPC分类号： H01L23/62

CPC分类号： H01L27/0277 ,  H01L29/0692 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/41758 ,  H01L29/4238 ,  H01L29/4975 ,  H01L29/78 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2924/00014

摘要： An electrostatic discharge (ESD) MOS transistor including a plurality of interleaved fingers, where the MOS transistor is formed in an I/O periphery of and integrated circuit (IC) for providing ESD protection for the IC. The MOS transistor includes a P-substrate and a Pwell disposed over the P-substrate. The plurality of interleaved fingers each include an N+ source region, an N+ drain region, and a gate region formed over a channel region disposed between the source and drain regions. Each source and drain includes a row of contacts that is shared by an adjacent finger, wherein each contact hole in each contact row has a distance to the gate region defined under minimum design rules for core functional elements of the IC. The Pwell forms a common parasitic bipolar junction transistor base for contemporaneously triggering each finger of the MOS transistor during an ESD event.

摘要翻译： 一种包括多个交错指状物的静电放电（ESD）MOS晶体管，其中MOS晶体管形成在用于IC的ESD保护的I / O外围和集成电路（IC）中。 MOS晶体管包括设置在P基板上的P基板和Pwell。 多个交错指状物各自包括N +源极区域，N +漏极区域和形成在设置在源极和漏极区域之间的沟道区域上的栅极区域。 每个源极和漏极包括由相邻手指共享的一排触点，其中每个触点行中的每个接触孔具有与IC的核心功能元件的最小设计规则下限定的栅极区域的距离。 Pwell形成一个公共寄生双极结晶体管基极，用于在ESD事件期间同时触发MOS晶体管的每个指状。

公开(公告)号：US06909149B2

公开(公告)日：2005-06-21

申请号：US10825780

申请日：2004-04-15

申请人： Cornelius Christian Russ ,  Phillip Czeslaw Jozwiak ,  Markus Paul Josef Mergens ,  John Armer ,  Cong-Son Trinh ,  Russell Mohn ,  Koen Gerard Maria Verhaege

发明人： Cornelius Christian Russ ,  Phillip Czeslaw Jozwiak ,  Markus Paul Josef Mergens ,  John Armer ,  Cong-Son Trinh ,  Russell Mohn ,  Koen Gerard Maria Verhaege

IPC分类号： H01L27/02 ,  H01L29/74 ,  H01L23/62

CPC分类号： H01L27/0262 ,  H01L29/7436

摘要： A silicon-on-insulator (SOI) electrostatic discharge (ESD) protection device that can protect very sensitive thin gate oxides by limiting the power dissipation during the ESD event, which is best achieved by reducing the voltage drop across the active (protection) device during an ESD event. In one embodiment, the invention provides very low triggering and holding voltages. Furthermore, the SOI protection device of the present invention has low impedance and low power dissipation characteristics that reduce voltage build-up, and accordingly, enable designers to fabricate more area efficient protection device

摘要翻译： 绝缘体上硅（SOI）静电放电（ESD）保护器件，可以通过限制ESD事件期间的功率损耗来保护非常敏感的薄栅极氧化物，这最好通过降低主动（保护）器件上的电压降来实现 在ESD事件期间。 在一个实施例中，本发明提供非常低的触发和保持电压。 此外，本发明的SOI保护器件具有低阻抗和低功耗特性，可减少电压的积聚，从而使设计者能够制造出更为面积更高的保护器件

公开(公告)号：US07064393B2

公开(公告)日：2006-06-20

申请号：US10783844

申请日：2004-02-20

申请人： Markus Paul Josef Mergens ,  Cornelius Christian Russ ,  John Armer ,  Koen Gerard Maria Verhaege ,  Phillip Czeslaw Jozwiak

发明人： Markus Paul Josef Mergens ,  Cornelius Christian Russ ,  John Armer ,  Koen Gerard Maria Verhaege ,  Phillip Czeslaw Jozwiak

IPC分类号： H01L23/62

CPC分类号： H01L27/0262 ,  H01L27/0292

摘要： An electrostatic discharge (ESD) protection device having high holding current for latch-up immunity. The ESD protection circuit is formed in a semiconductor integrated circuit (IC) having protected circuitry. The ESD protection device includes a silicon controlled rectifier (SCR) coupled between a protected supply line of the IC and ground. A trigger device is coupled from the supply line to a first gate of the SCR, and a first substrate resistor is coupled between the first gate and ground. A first shunt resistor is coupled between the first gate and ground, wherein the shunt resistor has a resistance value lower than the substrate resistor.

公开(公告)号：US06803633B2

公开(公告)日：2004-10-12

申请号：US10099263

申请日：2002-03-15

申请人： Markus Paul Josef Mergens ,  Cornelius Christian Russ ,  John Armer ,  Koen Gerard Maria Verhaege ,  Phillip Czeslaw Jozwiak

发明人： Markus Paul Josef Mergens ,  Cornelius Christian Russ ,  John Armer ,  Koen Gerard Maria Verhaege ,  Phillip Czeslaw Jozwiak

IPC分类号： H01L2362

CPC分类号： H01L27/0262 ,  H01L27/0292

摘要： An electrostatic discharge (ESD) protection device having high holding current for latch-up immunity. The ESD protection circuit is formed in a semiconductor integrated circuit (IC) having protected circuitry. The ESD protection device includes a silicon controlled rectifier (SCR) coupled between a protected supply line of the IC and ground. A trigger device is coupled from the supply line to a first gate of the SCR, and a first substrate resistor is coupled between the first gate and ground. A first shunt resistor is coupled between the first gate and ground, wherein the shunt resistor has a resistance value lower than the substrate resistor.

公开(公告)号：US06583972B2

公开(公告)日：2003-06-24

申请号：US09881422

申请日：2001-06-14

申请人： Koen Gerard Maria Verhaege ,  Markus Paul Josef Mergens ,  Cornelius Christian Russ ,  John Armer ,  Phillip Czeslaw Jozwiak

发明人： Koen Gerard Maria Verhaege ,  Markus Paul Josef Mergens ,  Cornelius Christian Russ ,  John Armer ,  Phillip Czeslaw Jozwiak

IPC分类号： H02H900

CPC分类号： H01L27/0266 ,  H01L2924/0002 ,  H01L2924/00

摘要： A multi-finger electro-static discharge (ESD) protection circuit has at least two first resistive channels defining input fingers. At least two field effect transistor (FET) channels, each having a drain and source are connected to corresponding ones of the at least two input fingers. The gate terminals of at least one of the at least two FETs are configured to be biased by an ESD potential applied to the drain electrodes to reduce the turn-on potential of the ESD device. At least two second resistive channels are connected between a corresponding one of the source terminals of the at least two FETs and a circuit return path.

公开(公告)号：US06770918B2

公开(公告)日：2004-08-03

申请号：US10238699

申请日：2002-09-10

申请人： Cornelius Christian Russ ,  John Armer ,  Markus Paul Josef Mergens ,  Phillip Czeslaw Jozwiak

发明人： Cornelius Christian Russ ,  John Armer ,  Markus Paul Josef Mergens ,  Phillip Czeslaw Jozwiak

IPC分类号： H01L2972

CPC分类号： H01L29/7436 ,  H01L27/0262 ,  H01L29/165 ,  H01L29/7378 ,  H01L29/861

摘要： An electrostatic discharge (ESD) protection device having a silicon controlled rectifier (SCR) for protecting circuitry of an integrated circuit (IC). The SCR includes a N-doped layer disposed over a substrate and a first P doped region disposed over the N-doped layer. At least one first N+ doped region forming a cathode is disposed over the P-doped region and coupled to ground. The at least one first N+ doped region, first P-doped region, and N-doped layer form a vertical NPN transistor of the SCR. A second P doped region forming an anode is coupled to a protected pad. The second P doped region is disposed over the N-doped layer, and is laterally positioned and electrically isolated with respect to the first P doped region. The second P doped region, N-doped layer, and first P doped region form a lateral PNP transistor of the SCR.

摘要翻译： 一种具有用于保护集成电路（IC）的电路的可控硅整流器（SCR）的静电放电（ESD）保护装置。 SCR包括设置在衬底上的N掺杂层和设置在N掺杂层上的第一P掺杂区。 形成阴极的至少一个第一N +掺杂区域设置在P掺杂区域上并耦合到地。 至少一个第一N +掺杂区，第一P掺杂区和N掺杂层形成SCR的垂直NPN晶体管。 形成阳极的第二P掺杂区域被耦合到受保护的焊盘。 第二P掺杂区域设置在N掺杂层上方，并相对于第一P掺杂区域横向定位并电隔离。 第二P掺杂区，N掺杂层和第一P掺杂区形成SCR的横向PNP晶体管。

公开(公告)号：US07372681B2

公开(公告)日：2008-05-13

申请号：US11105103

申请日：2005-04-13

申请人： John Armer ,  Markus Paul Josef Mergens ,  Phillip Czeslaw Jozwiak ,  Cornelius Christian Russ

发明人： John Armer ,  Markus Paul Josef Mergens ,  Phillip Czeslaw Jozwiak ,  Cornelius Christian Russ

IPC分类号： H02H9/00 ,  H02H3/20 ,  H02H9/04 ,  H02H1/00 ,  H02H1/04 ,  H02H3/22 ,  H02H9/06 ,  H01C7/12

CPC分类号： H01L29/0847 ,  H01L27/0266 ,  H01L29/0653 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrostatic discharge (ESD) protection circuit for a semiconductor integrated circuit (IC) that protects core circuitry of the IC during normal operations, and shunts ESD events during non-powered mode of the IC. The ESD protection circuitry includes a multi-fingered MOS transistor, each finger respectively adapted for coupling between an I/O pad and a first supply line of the IC. An ESD detector is coupled to the I/O pad via a first terminal, and a second terminal is adapted for coupling to a second supply line potential of the IC. A parasitic capacitance is formed between the second supply line potential of the IC and the first supply line potential. A transfer circuit is coupled to a third terminal of the ESD detector and is adapted for biasing at least one gate respectively associated with at least one finger of the multi-fingered MOS transistor.

摘要翻译： 用于在正常操作期间保护IC的核心电路的半导体集成电路（IC）的静电放电（ESD）保护电路，并且在IC的非供电模式期间分流ESD事件。 ESD保护电路包括多指MOS晶体管，每个手指分别适于在IC的I / O焊盘和第一电源线之间耦合。 ESD检测器经由第一端子耦合到I / O焊盘，并且第二端子适于耦合到IC的第二电源线电位。 在IC的第二供电线电位和第一供电线电位之间形成寄生电容。 传输电路耦合到ESD检测器的第三端子，并且适于偏置分别与多指MOS晶体管的至少一个手指相关联的至少一个栅极。

公开(公告)号：US07414273B2

公开(公告)日：2008-08-19

申请号：US11176975

申请日：2005-07-07

申请人： Russell Mohn ,  Cong-Son Trinh ,  Phillip Czeslaw Jozwiak ,  John Armer ,  Markus Paul Josef Mergens

发明人： Russell Mohn ,  Cong-Son Trinh ,  Phillip Czeslaw Jozwiak ,  John Armer ,  Markus Paul Josef Mergens

IPC分类号： H01L29/74 ,  H01L31/111

CPC分类号： H01L29/7436 ,  H01L27/0259 ,  H01L27/0262 ,  H01L29/0692 ,  H01L29/74 ,  H01L29/87

摘要： A two-dimensional silicon controlled rectifier (2DSCR) having the anode and cathode forming a checkerboard pattern. Such a pattern maximizes the anode to cathode contact length (the active area) within a given SCR area, i.e., effectively increasing the SCR width. Increasing the physical SCR area, increases the current handling capabilities of the SCR.

摘要翻译： 具有形成棋盘图案的阳极和阴极的二维可控硅整流器（2DSCR）。 这种图案使给定SCR区域内的阳极与阴极接触长度（有效面积）最大化，即有效地增加SCR宽度。 增加物理SCR区域，增加SCR的当前处理能力。

公开(公告)号：US06898062B2

公开(公告)日：2005-05-24

申请号：US10822912

申请日：2004-04-12

申请人： Cornelius Christian Russ ,  John Armer ,  Markus Paul Josef Mergens ,  Phillip Czeslaw Jozwiak

发明人： Cornelius Christian Russ ,  John Armer ,  Markus Paul Josef Mergens ,  Phillip Czeslaw Jozwiak

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H02H9/00

CPC分类号： H01L29/0847 ,  H01L27/0266 ,  H01L29/0653 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： An ESD protection circuit for a semiconductor integrated circuit (IC) having protected circuitry, includes an SCR having at least one finger. Each finger includes a PNP transistor and an NPN transistor, where an emitter of the PNP and NPN transistors is respectively coupled between an I/O pad of the IC and ground, a base of the PNP transistor being coupled to a collector of the NPN transistor, and a base of the NPN transistor being coupled to a collector of the PNP transistor. The NPN transistor of each finger further includes a first gate for triggering said finger. A PMOS transistor includes a source and a drain respectively coupled to the I/O pad of the IC and the first gate of the NPN transistor. Further, a gate of the PMOS transistor is coupled to a supply voltage of the IC.

摘要翻译： 具有受保护电路的半导体集成电路（IC）的ESD保护电路包括具有至少一个手指的SCR。 每个手指包括PNP晶体管和NPN晶体管，其中PNP和NPN晶体管的发射极分别耦合在IC的I / O焊盘和地之间，PNP晶体管的基极耦合到NPN晶体管的集电极 ，并且NPN晶体管的基极耦合到PNP晶体管的集电极。 每个手指的NPN晶体管还包括用于触发所述手指的第一门。 PMOS晶体管包括分别耦合到IC的I / O焊盘和NPN晶体管的第一栅极的源极和漏极。 此外，PMOS晶体管的栅极耦合到IC的电源电压。