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    Split gate power device and its method of fabrication
    1.
    发明授权
    Split gate power device and its method of fabrication 有权

    公开(公告)号：US11289596B2

    公开(公告)日：2022-03-29

    申请号：US16782996

    申请日：2020-02-05

    Applicant: MaxPower Semiconductor Inc.

    Inventor： Jun Zeng ,  Kui Pu ,  Mohamed N. Darwish ,  Shih-Tzung Su

    IPC: H01L29/78 ,  H01L29/40 ,  H01L29/66 ,  H01L29/08 ,  H01L29/417

    Abstract: A split gate power device is disclosed having a trench containing a U-shaped gate that, when biased above a threshold voltage, creates a conductive channel in a p-well. Below the gate is a field plate in the trench, coupled to the source electrode, for spreading the electric field along the trench to improve the breakdown voltage. The top gate poly is initially formed relatively thin so that it can be patterned using non-CMP techniques, such as dry etching or wet etching. As such, the power device can be fabricated in conventional fabs not having CMP capability. In one embodiment, the thin gate has vertical and lateral portions that create conductive vertical and lateral channels in a p-well. In another embodiment, the thin gate has only vertical portions along the trench sidewalls for minimizing surface area and gate capacitance.

    MOSFET with distributed doped P-shield zones under trenches
    3.
    发明授权
    MOSFET with distributed doped P-shield zones under trenches 有权

    公开(公告)号：US12057482B2

    公开(公告)日：2024-08-06

    申请号：US17395239

    申请日：2021-08-05

    Applicant: MaxPower Semiconductor, Inc.

    Inventor： Jun Zeng ,  Mohamed N. Darwish ,  Shih-Tzung Su

    IPC: H01L29/423 ,  H01L23/60 ,  H01L29/66 ,  H01L29/78

    CPC classification number: H01L29/4236 ,  H01L23/60 ,  H01L29/66719 ,  H01L29/66734 ,  H01L29/7813

    Abstract: A vertical trench MOSFET is formed with deep P-shield regions below portions of each gate trench. The deep P-shield regions are effectively downward extensions of the P-body/well, and are electrically coupled to the top source electrode. The P-shield regions abut the bottom portions and lower sides of the gate trenches, so that those small portions of the gate trench do not create N-channels and do not conduct current. Accordingly, each trench comprises an active gate portion that creates an N-channel and a small non-active portion that abuts the P-shield regions. The spacing of the P-shield regions along each gate trench is selected to achieve the desired electric field spreading to protect the gate oxide from punch-through. No field plate trenches are needed to be formed in the active area of the MOSFET. The deep P-shield regions are formed by implanting P-type dopants through the bottom of the trenches.

    SPLIT GATE POWER DEVICE AND ITS METHOD OF FABRICATION
    4.
    发明申请
    SPLIT GATE POWER DEVICE AND ITS METHOD OF FABRICATION 审中-公开

    公开(公告)号：US20200273987A1

    公开(公告)日：2020-08-27

    申请号：US16782996

    申请日：2020-02-05

    Applicant: MaxPower Semiconductor Inc.

    Inventor： Jun Zeng ,  Kui Pu ,  Mohamed N. Darwish ,  Shih-Tzung Su

    IPC: H01L29/78 ,  H01L29/40 ,  H01L29/66 ,  H01L29/08 ,  H01L29/417

    Abstract: A split gate power device is disclosed having a trench containing a U-shaped gate that, when biased above a threshold voltage, creates a conductive channel in a p-well. Below the gate is a field plate in the trench, coupled to the source electrode, for spreading the electric field along the trench to improve the breakdown voltage. The top gate poly is initially formed relatively thin so that it can be patterned using non-CMP techniques, such as dry etching or wet etching. As such, the power device can be fabricated in conventional fabs not having CMP capability. In one embodiment, the thin gate has vertical and lateral portions that create conductive vertical and lateral channels in a p-well. In another embodiment, the thin gate has only vertical portions along the trench sidewalls for minimizing surface area and gate capacitance.

    POWER MOSFET HAVING PLANAR CHANNEL, VERTICAL CURRENT PATH, AND TOP DRAIN ELECTRODE
    9.
    发明申请
    POWER MOSFET HAVING PLANAR CHANNEL, VERTICAL CURRENT PATH, AND TOP DRAIN ELECTRODE 有权
    功率MOSFET具有平面通道，垂直电流通道和顶部漏极电极

    公开(公告)号：US20160359029A1

    公开(公告)日：2016-12-08

    申请号：US15240831

    申请日：2016-08-18

    Applicant: MaxPower Semiconductor, Inc.

    Inventor： Jun Zeng ,  Mohamed N. Darwish ,  Kui Pu ,  Shih-Tzung Su

    IPC: H01L29/739 ,  H01L29/66 ,  H01L29/10 ,  H01L29/423 ,  H01L29/40 ,  H01L29/78

    CPC classification number: H01L29/7397 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813

    Abstract: In one embodiment, a power MOSFET cell includes an N+ silicon substrate having a drain electrode. An N-type drift layer is grown over the substrate. An N-type layer, having a higher dopant concentration than the drift region, is then formed along with a trench having sidewalls. A P-well is formed in the N-type layer, and an N+ source region is formed in the P-well. A gate is formed over the P-well's lateral channel and has a vertical extension into the trench. A positive gate voltage inverts the lateral channel and increases the vertical conduction along the sidewalls to reduce on-resistance. A vertical shield field plate is also located next to the sidewalls and may be connected to the gate. The field plate laterally depletes the N-type layer when the device is off to increase the breakdown voltage. A buried layer and sinker enable the use of a topside drain electrode.

    Abstract translation: 在一个实施例中，功率MOSFET单元包括具有漏电极的N +硅衬底。 在衬底上生长N型漂移层。 然后与具有侧壁的沟槽一起形成具有比漂移区更高的掺杂剂浓度的N型层。 在N型层中形成P阱，在P阱中形成N +源极区。 门形成在P阱的横向通道上，并且具有垂直延伸到沟槽中。 正栅极电压反转横向沟道并增加沿着侧壁的垂直传导以降低导通电阻。 垂直屏蔽场板也位于侧壁旁边，并且可以连接到门。 当设备关闭时，场板横向耗尽N型层以增加击穿电压。 掩埋层和沉降片使得能够使用顶侧漏电极。

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