公开(公告)号：US11289596B2

公开(公告)日：2022-03-29

申请号：US16782996

申请日：2020-02-05

Applicant: MaxPower Semiconductor Inc.

Inventor： Jun Zeng ,  Kui Pu ,  Mohamed N. Darwish ,  Shih-Tzung Su

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/66 ,  H01L29/08 ,  H01L29/417

Abstract: A split gate power device is disclosed having a trench containing a U-shaped gate that, when biased above a threshold voltage, creates a conductive channel in a p-well. Below the gate is a field plate in the trench, coupled to the source electrode, for spreading the electric field along the trench to improve the breakdown voltage. The top gate poly is initially formed relatively thin so that it can be patterned using non-CMP techniques, such as dry etching or wet etching. As such, the power device can be fabricated in conventional fabs not having CMP capability. In one embodiment, the thin gate has vertical and lateral portions that create conductive vertical and lateral channels in a p-well. In another embodiment, the thin gate has only vertical portions along the trench sidewalls for minimizing surface area and gate capacitance.

公开(公告)号：US09947779B2

公开(公告)日：2018-04-17

申请号：US15663465

申请日：2017-07-28

Applicant: MaxPower Semiconductor Inc.

Inventor： Jun Zeng ,  Mohamed N. Darwish ,  Kui Pu ,  Shih-Tzung Su

IPC: H01L29/739 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/40 ,  H01L29/78 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L29/7397 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813

Abstract: In one embodiment, a power MOSFET cell includes an N+ silicon substrate having a drain electrode. An N-type drift layer is grown over the substrate. An N-type layer, having a higher dopant concentration than the drift region, is then formed along with a trench having sidewalls. A P-well is formed in the N-type layer, and an N+ source region is formed in the P-well. A gate is formed over the P-well's lateral channel and has a vertical extension into the trench. A positive gate voltage inverts the lateral channel and increases the vertical conduction along the sidewalls to reduce on-resistance. A vertical shield field plate is also located next to the sidewalls and may be connected to the gate. The field plate laterally depletes the N-type layer when the device is off to increase the breakdown voltage. A buried layer and sinker enable the use of a topside drain electrode.

公开(公告)号：US20200273987A1

公开(公告)日：2020-08-27

申请号：US16782996

申请日：2020-02-05

Applicant: MaxPower Semiconductor Inc.

Inventor： Jun Zeng ,  Kui Pu ,  Mohamed N. Darwish ,  Shih-Tzung Su

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/66 ,  H01L29/08 ,  H01L29/417

Abstract: A split gate power device is disclosed having a trench containing a U-shaped gate that, when biased above a threshold voltage, creates a conductive channel in a p-well. Below the gate is a field plate in the trench, coupled to the source electrode, for spreading the electric field along the trench to improve the breakdown voltage. The top gate poly is initially formed relatively thin so that it can be patterned using non-CMP techniques, such as dry etching or wet etching. As such, the power device can be fabricated in conventional fabs not having CMP capability. In one embodiment, the thin gate has vertical and lateral portions that create conductive vertical and lateral channels in a p-well. In another embodiment, the thin gate has only vertical portions along the trench sidewalls for minimizing surface area and gate capacitance.

公开(公告)号：US09461127B2

公开(公告)日：2016-10-04

申请号：US14873103

申请日：2015-10-01

Applicant: MaxPower Semiconductor, Inc.

Inventor： Jun Zeng ,  Mohamed N. Darwish ,  Kui Pu ,  Shih-Tzung Su

IPC: H01L29/40 ,  H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L29/739 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/407 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7395 ,  H01L29/7396 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813

Abstract: A power MOSFET cell includes an N+ silicon substrate having a drain electrode. A low dopant concentration N-type drift layer is grown over the substrate. An N-type layer, having a higher dopant concentration than the drift region, is then formed and etched to have sidewalls. A P-well is formed in the N-type layer, and an N+ source region is formed in the P-well. A gate is formed over the P-well's lateral channel and has a vertical extension next to the top portion of the sidewalls. A positive gate voltage inverts the lateral channel and increases the conduction along the sidewalls to reduce on-resistance. A vertical shield field plate is also located next to the sidewalls and extends virtually the entire length of the sidewalls. The field plate laterally depletes the N-type layer when the device is off to increase the breakdown voltage.

公开(公告)号：US20160027880A1

公开(公告)日：2016-01-28

申请号：US14873103

申请日：2015-10-01

Applicant: MaxPower Semiconductor, Inc.

Inventor： Jun Zeng ,  Mohamed N. Darwish ,  Kui Pu ,  Shih-Tzung Su

IPC: H01L29/40 ,  H01L29/423 ,  H01L29/10 ,  H01L29/78 ,  H01L29/739

CPC classification number: H01L29/407 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7395 ,  H01L29/7396 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813

Abstract: A power MOSFET cell includes an N+ silicon substrate having a drain electrode. A low dopant concentration N-type drift layer is grown over the substrate. An N-type layer, having a higher dopant concentration than the drift region, is then formed and etched to have sidewalls. A P-well is formed in the N-type layer, and an N+ source region is formed in the P-well. A gate is formed over the P-well's lateral channel and has a vertical extension next to the top portion of the sidewalls. A positive gate voltage inverts the lateral channel and increases the conduction along the sidewalls to reduce on-resistance. A vertical shield field plate is also located next to the sidewalls and extends virtually the entire length of the sidewalls. The field plate laterally depletes the N-type layer when the device is off to increase the breakdown voltage.

公开(公告)号：US20180261666A1

公开(公告)日：2018-09-13

申请号：US15894811

申请日：2018-02-12

Applicant: MaxPower Semiconductor Inc.

Inventor： Jun Zeng ,  Mohamed N. Darwish ,  Wenfang Du ,  Richard A. Blanchard ,  Kui Pu ,  Shih-Tzung Su

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L29/739 ,  H01L29/78

CPC classification number: H01L29/0634 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/7397 ,  H01L29/7813

Abstract: In one embodiment, a power MOSFET or IGBT cell includes an N-type drift region grown over the substrate. An N-type layer, having a higher dopant concentration than the drift region, is then formed over the drift region. A P-well is formed over the N-type layer, and an N+ source/emitter region is formed in the P-well. A gate is formed over the P-well's lateral channel and has a vertical extension into a trench. A positive gate voltage inverts the lateral channel and increases the vertical conduction in the N-type layer along the sidewalls of the trench to reduce on-resistance. A vertical shield field plate is also in the trench and may be connected to the gate. The field plate laterally depletes the N-type layer when the device is off to increase the breakdown voltage. Floating P-islands in the N-type drift region increase breakdown voltage and reduce the saturation current.

公开(公告)号：US09761702B2

公开(公告)日：2017-09-12

申请号：US15240831

申请日：2016-08-18

Applicant: MaxPower Semiconductor, Inc.

Inventor： Jun Zeng ,  Mohamed N. Darwish ,  Kui Pu ,  Shih-Tzung Su

IPC: H01L29/739 ,  H01L29/08 ,  H01L29/40 ,  H01L29/06 ,  H01L29/78 ,  H01L29/423 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/7397 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813

Abstract: In one embodiment, a power MOSFET cell includes an N+ silicon substrate having a drain electrode. An N-type drift layer is grown over the substrate. An N-type layer, having a higher dopant concentration than the drift region, is then formed along with a trench having sidewalls. A P-well is formed in the N-type layer, and an N+ source region is formed in the P-well. A gate is formed over the P-well's lateral channel and has a vertical extension into the trench. A positive gate voltage inverts the lateral channel and increases the vertical conduction along the sidewalls to reduce on-resistance. A vertical shield field plate is also located next to the sidewalls and may be connected to the gate. The field plate laterally depletes the N-type layer when the device is off to increase the breakdown voltage. A buried layer and sinker enable the use of a topside drain electrode.

公开(公告)号：US20150221731A1

公开(公告)日：2015-08-06

申请号：US14616395

申请日：2015-02-06

Applicant: MaxPower Semiconductor, Inc.

Inventor： Jun Zeng ,  Mohamed N. Darwish ,  Kui Pu ,  Shih-Tzung Su

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/739 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/407 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7395 ,  H01L29/7396 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813

Abstract: A power MOSFET cell includes an N+ silicon substrate having a drain electrode. A low dopant concentration N-type drift layer is grown over the substrate. An N-type layer, having a higher dopant concentration than the drift region, is then formed and etched to have sidewalls. A P-well is formed in the N-type layer, and an N+ source region is formed in the P-well. A gate is formed over the P-well's lateral channel and has a vertical extension next to the top portion of the sidewalls. A positive gate voltage inverts the lateral channel and increases the conduction along the sidewalls to reduce on-resistance. A vertical shield field plate is also located next to the sidewalls and extends virtually the entire length of the sidewalls. The field plate laterally depletes the N-type layer when the device is off to increase the breakdown voltage.

Abstract translation: 功率MOSFET单元包括具有漏电极的N +硅衬底。 在衬底上生长低掺杂浓度的N型漂移层。 然后形成具有比漂移区更高的掺杂剂浓度的N型层并蚀刻以具有侧壁。 在N型层中形成P阱，在P阱中形成N +源极区。 栅极形成在P阱的横向通道上，并且具有靠近侧壁顶部的垂直延伸。 正栅极电压反转横向沟道并增加沿侧壁的导通以降低导通电阻。 垂直屏蔽场板也位于侧壁旁边，几乎延伸到侧壁的整个长度上。 当设备关闭时，场板横向耗尽N型层以增加击穿电压。

公开(公告)号：US09093522B1

公开(公告)日：2015-07-28

申请号：US14338303

申请日：2014-07-22

Applicant: MaxPower Semiconductor, Inc.

Inventor： Jun Zeng ,  Mohamed N. Darwish ,  Kui Pu ,  Shih-Tzung Su

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/732 ,  H01L29/739 ,  H01L29/40 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L29/7813 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0834 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/6634 ,  H01L29/66348 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7396 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7811

Abstract: A power MOSFET cell includes an N+ silicon substrate having a drain electrode. A low dopant concentration N-type drift layer is grown over the substrate. Alternating N and P-type columns are formed over the drift layer with a higher dopant concentration. An N-type layer, having a higher dopant concentration than the drift region, is then formed and etched to have sidewalls. A P-well is formed in the N-type layer, and an N+ source region is formed in the P-well. A gate is formed over the P-well's lateral channel and next to the sidewalls as a vertical field plate. A source electrode contacts the P-well and source region. A positive gate voltage inverts the lateral channel and increases the conduction along the sidewalls. Current between the source and drain flows laterally and then vertically through the various N layers. On resistance is reduced and the breakdown voltage is increased.

Abstract translation: 功率MOSFET单元包括具有漏电极的N +硅衬底。 在衬底上生长低掺杂浓度的N型漂移层。 在漂移层上形成交替的N型和P型列，掺杂浓度较高。 然后形成具有比漂移区更高的掺杂剂浓度的N型层并蚀刻以具有侧壁。 在N型层中形成P阱，在P阱中形成N +源极区。 在P阱的横向通道上形成一个栅极，并且在侧壁上形成一个垂直场板。 源电极接触P阱和源极区。 正栅极电压反转横向沟道并增加沿着侧壁的导电。 源极和漏极之间的电流横向流动，然后垂直穿过各种N层。 导通电阻降低，击穿电压增加。

公开(公告)号：US10157983B2

公开(公告)日：2018-12-18

申请号：US15894811

申请日：2018-02-12

Applicant: MaxPower Semiconductor Inc.

Inventor： Jun Zeng ,  Mohamed N. Darwish ,  Wenfang Du ,  Richard A. Blanchard ,  Kui Pu ,  Shih-Tzung Su

IPC: H01L29/02 ,  H01L29/06 ,  H01L29/10 ,  H01L29/78 ,  H01L29/423 ,  H01L29/739 ,  H01L29/40

Abstract: In one embodiment, a power MOSFET or IGBT cell includes an N-type drift region grown over the substrate. An N-type layer, having a higher dopant concentration than the drift region, is then formed over the drift region. A P-well is formed over the N-type layer, and an N+ source/emitter region is formed in the P-well. A gate is formed over the P-well's lateral channel and has a vertical extension into a trench. A positive gate voltage inverts the lateral channel and increases the vertical conduction in the N-type layer along the sidewalls of the trench to reduce on-resistance. A vertical shield field plate is also in the trench and may be connected to the gate. The field plate laterally depletes the N-type layer when the device is off to increase the breakdown voltage. Floating P-islands in the N-type drift region increase breakdown voltage and reduce the saturation current.