公开(公告)号：US20240112963A1

公开(公告)日：2024-04-04

申请号：US18366914

申请日：2023-08-08

Applicant: MEDIATEK INC.

Inventor： Yu-Tung CHEN ,  Pei-Haw TSAO ,  Kuo-Lung FAN ,  Yuan-Fu CHUNG

IPC: H01L21/66

CPC classification number: H01L22/32

Abstract: A semiconductor structure is provided. The semiconductor structure includes a semiconductor wafer and a test structure. The semiconductor wafer has a substrate having a scribe line area, a first die area and a second die area. The first die area and the second die area are separated by the scribe line area extending along a first direction. The test structure is disposed in the scribe line area. The test structure includes a test device and a first test pad. The test device has a physical characteristic similar to a semiconductor device fabricated in the first die area or the second die area. The first test pad is electrically connected to the test device. A first distance between the first test pad and the first die area gradually increases from a center region to a peripheral region of the first test pad in the first direction.

公开(公告)号：US20150187757A1

公开(公告)日：2015-07-02

申请号：US14557743

申请日：2014-12-02

Applicant: MediaTek Inc.

Inventor： Yuan-Fu CHUNG ,  Chu-Wei HU ,  Yuan-Hung CHUNG

IPC: H01L27/06 ,  H01L29/49 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/265 ,  H01L21/268 ,  H01L21/324 ,  H01L21/762 ,  H01L49/02 ,  H01L21/28

CPC classification number: H01L28/20 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/268 ,  H01L21/28035 ,  H01L21/32155 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/8234 ,  H01L21/823437 ,  H01L27/0207 ,  H01L27/0629 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/167 ,  H01L29/4916

Abstract: An integrated circuit includes a first polysilicon region having a first grain size formed on a substrate. The integrated circuit also includes a second polysilicon region, having a second grain size different from the first grain size, formed on the substrate. Furthermore, a method of fabricating an integrated circuit is also provided. The method includes forming a first polysilicon region having an initial grain size on a substrate. The first polysilicon region is implanted with a first dopant of a first conductivity type and a second dopant. After the implantation, the first polysilicon region has a first grain size larger than the initial grain size. Then, a laser rapid thermal annealing process is performed to the first polysilicon region.

Abstract translation: 集成电路包括在基板上形成的具有第一晶粒尺寸的第一多晶硅区域。 集成电路还包括形成在基板上的具有与第一晶粒尺寸不同的第二晶粒尺寸的第二多晶硅区域。 此外，还提供了一种制造集成电路的方法。 该方法包括在衬底上形成具有初始晶粒尺寸的第一多晶硅区域。 第一多晶硅区域注入第一导电类型的第一掺杂剂和第二掺杂剂。 在注入之后，第一多晶硅区域具有比初始晶粒尺寸大的第一晶粒尺寸。 然后，对第一多晶硅区域进行激光快速热退火处理。

公开(公告)号：US20240339447A1

公开(公告)日：2024-10-10

申请号：US18603426

申请日：2024-03-13

Applicant: MEDIATEK INC.

Inventor： Tzung-Lin LI ,  Yuan-Fu CHUNG ,  Tung-Hsing LEE

IPC: H01L27/02 ,  H01L29/868

CPC classification number: H01L27/0255 ,  H01L29/868

Abstract: An electrostatic discharge protection device is provided. The electrostatic discharge protection device includes a P-type semiconductor substrate, P-type and N-type well regions, a deep N-type well region, first N-type and P-type doped regions, second N-type and P-type doped regions. The P-type and N-type well regions are located in the P-type semiconductor substrate. The deep N-type well region is located in the P-type semiconductor substrate and below the P-type well region. The first N-type and P-type doped regions are located on the P-type well region. The second N-type and P-type doped regions are located on the N-type well region. The first P-type doped region is electrically connected to the second N-type doped region.

公开(公告)号：US20230061138A1

公开(公告)日：2023-03-02

申请号：US17816749

申请日：2022-08-02

Applicant: MEDIATEK INC.

Inventor： Yu-Lin YANG ,  Ming-Cheng LEE ,  Yuan-Fu CHUNG

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/51 ,  H01L21/8234

Abstract: A semiconductor device structure includes a semiconductor substrate, a first device formed in the first region of the semiconductor substrate and a second device formed in the second region of the semiconductor substrate. The first device includes a first gate structure on the semiconductor substrate. The first gate structure includes a first gate dielectric layer on the semiconductor substrate and a first gate layer on the first gate dielectric layer. The second device includes a second gate structure on the semiconductor substrate. The second gate structure includes a second gate dielectric layer on the semiconductor substrate and a second gate layer on the second gate dielectric layer. The first gate dielectric layer of the first device and the second gate dielectric layer of the second device have different dielectric material compositions.

公开(公告)号：US20170229442A1

公开(公告)日：2017-08-10

申请号：US15495185

申请日：2017-04-24

Applicant: MediaTek Inc.

Inventor： Chien-Kai HUANG ,  Yuan-Fu CHUNG ,  Bo-Shih HUANG ,  Chang-Tzu WANG

IPC: H01L27/02 ,  H01L29/861 ,  H01L29/06

CPC classification number: H01L27/0255 ,  H01L27/0296 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/0692 ,  H01L29/8611

Abstract: A semiconductor device includes a semiconductor substrate and a pair of first well regions formed in the semiconductor substrate, wherein the pair of first well regions have a first conductivity type and are separated by at least one portion of the semiconductor substrate. The semiconductor device also includes a first doping region formed in a portion of at least one portion of the semiconductor substrate separating the pair of first well regions, and a pair of second doping regions, respectively formed in one of the pair of first well regions, having the first conductivity type. Further, the semiconductor device includes a pair of insulating layers, respectively formed over a portion of the semiconductor substrate to cover a portion of the first doped region and one of the pair of second doping regions.

公开(公告)号：US20160276338A1

公开(公告)日：2016-09-22

申请号：US15167783

申请日：2016-05-27

Applicant: MediaTek Inc.

Inventor： Yuan-Fu CHUNG ,  Chu-Wei HU ,  Yuan-Hung CHUNG

IPC: H01L27/06 ,  H01L29/49 ,  H01L21/324 ,  H01L21/3215 ,  H01L21/265 ,  H01L21/8234 ,  H01L49/02 ,  H01L29/06

CPC classification number: H01L28/20 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/268 ,  H01L21/28035 ,  H01L21/32155 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/8234 ,  H01L21/823437 ,  H01L27/0207 ,  H01L27/0629 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/167 ,  H01L29/4916

Abstract: An integrated circuit includes a first polysilicon region having a first grain size formed on a substrate. The integrated circuit also includes a second polysilicon region, having a second grain size different from the first grain size, formed on the substrate. The first polysilicon region is doped with a first dopant of a first conductive type and a second dopant selected from elements of group IIIA and group IVA which has an atomic weight heavier than that of silicon.

Abstract translation: 集成电路包括在基板上形成的具有第一晶粒尺寸的第一多晶硅区域。 集成电路还包括形成在基板上的具有与第一晶粒尺寸不同的第二晶粒尺寸的第二多晶硅区域。 第一多晶硅区域掺杂有第一导电类型的第一掺杂剂和选自原子量比硅重量的IIIA族和IVA族元素的第二掺杂物。

公开(公告)号：US20160141285A1

公开(公告)日：2016-05-19

申请号：US14884981

申请日：2015-10-16

Applicant: MediaTek Inc.

Inventor： Chien-Kai HUANG ,  Yuan-Fu CHUNG ,  Bo-Shih HUANG ,  Chang-Tzu WANG

IPC: H01L27/02 ,  H01L29/06 ,  H01L29/861

CPC classification number: H01L27/0255 ,  H01L27/0296 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/8611

Abstract: An electrostatic discharge (ESD) protection device includes a semiconductor substrate and a pair of first well regions formed in the semiconductor substrate, wherein the pair of first well regions have a first conductivity type and are separated by at least one portion of the semiconductor substrate. In addition, the ESD protection device further includes a first doping region formed in a portion of the at least one portion of the semiconductor substrate separating the pair of first well regions, having a second conductivity type opposite to the first conductivity type. Moreover, the ESD protection device further includes a pair of second doping regions respectively formed in one of the first well regions, having the first conductivity type, and a pair of insulating layers respectively formed over a portion of the semiconductor substrate to cover a portion of the first doped region and one of the second doping regions.

Abstract translation: 静电放电（ESD）保护装置包括半导体衬底和形成在半导体衬底中的一对第一阱区，其中该一对第一阱区具有第一导电类型并由半导体衬底的至少一部分分隔开。 此外，ESD保护装置还包括形成在半导体衬底的至少一部分的一部分中的第一掺杂区域，该半导体衬底的一部分与第一导电类型相反地具有第二导电类型。 此外，ESD保护装置还包括分别形成在具有第一导电类型的第一阱区域中的一个中的一对第二掺杂区域和分别形成在半导体衬底的一部分上以覆盖部分的一对绝缘层 第一掺杂区和第二掺杂区中的一个。

公开(公告)号：US20160043162A1

公开(公告)日：2016-02-11

申请号：US14886221

申请日：2015-10-19

Applicant: MediaTek Inc.

Inventor： Yuan-Fu CHUNG ,  Chu-Wei HU ,  Yuan-Hung CHUNG

IPC: H01L49/02 ,  H01L21/265 ,  H01L29/167 ,  H01L21/324 ,  H01L21/268 ,  H01L21/266 ,  H01L29/06 ,  H01L27/06 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/28

CPC classification number: H01L28/20 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/268 ,  H01L21/28035 ,  H01L21/32155 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/8234 ,  H01L21/823437 ,  H01L27/0207 ,  H01L27/0629 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/167 ,  H01L29/4916

Abstract: A method of fabricating an integrated circuit is also provided. The method includes forming a first polysilicon region having an initial grain size on a substrate. The first polysilicon region is implanted with a first dopant of a first conductivity type and a second dopant. After the implantation, the first polysilicon region has a first grain size larger than the initial grain size. Then, a laser rapid thermal annealing process is performed to the first polysilicon region.

Abstract translation: 还提供了一种制造集成电路的方法。 该方法包括在衬底上形成具有初始晶粒尺寸的第一多晶硅区域。 第一多晶硅区域注入第一导电类型的第一掺杂剂和第二掺杂剂。 在注入之后，第一多晶硅区域具有比初始晶粒尺寸大的第一晶粒尺寸。 然后，对第一多晶硅区域进行激光快速热退火处理。