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1.发明授权公开(公告)号：US09590610B2
公开(公告)日：2017-03-07
申请号：US14822913
申请日：2015-08-11
Applicant: MEDIATEK INC.
Inventor： Yan-Bin Luo , Chien-Hua Wu , Chung-Shi Lin , Chih-Hsien Lin
CPC classification number: H03K17/10 , H04L25/0272 , H04L25/0282 , H04L25/4906
Abstract: A driver circuit for receiving input data and generating an output signal to a termination element is disclosed, wherein the input data has a first bit and second bit, and the driver circuit includes: a pair of differential output terminals, arranged for outputting the output signal, wherein the pair of differential output terminals has a first output terminal and a second output terminal; a current mode drive unit, coupled to the pair of differential output terminals, for outputting a current from one of the first output terminal and the second output terminal, and receiving the current from the other of the first output terminal and the second output terminal according to the first bit; and a voltage mode drive unit, coupled to the pair of differential output terminals, for providing voltages to the first output terminal and the second output terminal according to at least the second bit.
Abstract translation: 公开了一种用于接收输入数据并向终端元件产生输出信号的驱动电路，其中输入数据具有第一位和第二位，并且驱动电路包括：一对差分输出端，用于输出输出信号 ，其中所述一对差分输出端子具有第一输出端子和第二输出端子; 电流模式驱动单元，耦合到所述一对差分输出端子，用于从所述第一输出端子和所述第二输出端子之一输出电流，以及根据所述第一输出端子和所述第二输出端子中的另一个接收所述电流， 到第一位 以及耦合到所述一对差分输出端子的电压模式驱动单元，用于根据至少所述第二位向所述第一输出端子和所述第二输出端子提供电压。
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公开(公告)号：US20140145708A1
公开(公告)日：2014-05-29
申请号：US14078548
申请日：2013-11-13
Applicant: MEDIATEK INC.
Inventor： Chien-Hua Wu , Kuan-Hua Chao
IPC: G01R19/00
CPC classification number: G06F11/221 , G06F11/2215 , G06F11/2247
Abstract: A detecting circuit includes: a testing signal generator, arranged to selectively generate a testing signal having a first signal edge or a second signal edge to a connecting port; and a detector, arranged to detect a first detect signal on the connecting port after the testing signal having the first signal edge is coupled to the connecting port, and to detect a second detect signal on the connecting port after the testing signal having the second signal edge is coupled to the connecting port; wherein the detector is further arranged to determine if an external circuit element is coupled between the connecting port and a reference voltage according to the first detect signal and the second detect signal.
Abstract translation: 检测电路包括：测试信号发生器，被布置成选择性地产生具有第一信号边缘或第二信号边缘的测试信号到连接端口; 以及检测器，被布置成在具有第一信号边缘的测试信号耦合到连接端口之后检测连接端口上的第一检测信号，并且在具有第二信号的测试信号之后检测连接端口上的第二检测信号 边缘连接到连接端口; 其中所述检测器还被布置成根据所述第一检测信号和所述第二检测信号来确定外部电路元件是否连接在所述连接端口和参考电压之间。
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公开(公告)号：US09590595B2
公开(公告)日：2017-03-07
申请号：US14825149
申请日：2015-08-12
Applicant: MEDIATEK INC.
Inventor： Yan-Bin Luo , Chien-Hua Wu , Chung-Shi Lin , Chih-Hsien Lin
IPC: H03K17/10 , H03K3/012 , H03K19/0185 , H04L25/03 , H03K19/0175
CPC classification number: H03K3/012 , H03K19/017509 , H03K19/018528 , H03K19/018585 , H04L25/03076
Abstract: A driver circuit for receiving input data and generating an output signal to a termination element is provided, wherein the input data has a first bit and second bit, and the driver circuit includes: a pair of differential output terminals for outputting the output signal, wherein the pair of differential output terminals has a first output terminal and a second output terminal; at least one current mode drive unit, coupled to the pair of differential output terminals, for outputting a current from one of the first output terminal and the second output terminal, and receiving the current from the other of the first output terminal and the second output terminal according to the first bit; and at least one voltage mode drive unit, coupled to the pair of differential output terminals, for providing voltages to the first output terminal and the second output terminal according to the second bit.
Abstract translation: 提供了一种用于接收输入数据并向终端元件产生输出信号的驱动电路，其中输入数据具有第一位和第二位，并且驱动电路包括：一对差分输出端，用于输出输出信号，其中 一对差分输出端子具有第一输出端子和第二输出端子; 耦合到所述一对差分输出端子的至少一个电流模式驱动单元，用于从所述第一输出端子和所述第二输出端子之一输出电流，以及从所述第一输出端子和所述第二输出端子中的另一个接收电流 终端根据第一位; 以及耦合到所述一对差分输出端子的至少一个电压模式驱动单元，用于根据所述第二位向所述第一输出端子和所述第二输出端子提供电压。
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4.发明申请公开(公告)号：US20160191037A1
公开(公告)日：2016-06-30
申请号：US14822913
申请日：2015-08-11
Applicant: MEDIATEK INC.
Inventor： Yan-Bin Luo , Chien-Hua Wu , Chung-Shi Lin , Chih-Hsien Lin
IPC: H03K17/10
CPC classification number: H03K17/10 , H04L25/0272 , H04L25/0282 , H04L25/4906
Abstract: A driver circuit for receiving input data and generating an output signal to a termination element is disclosed, wherein the input data has a first bit and second bit, and the driver circuit includes: a pair of differential output terminals, arranged for outputting the output signal, wherein the pair of differential output terminals has a first output terminal and a second output terminal; a current mode drive unit, coupled to the pair of differential output terminals, for outputting a current from one of the first output terminal and the second output terminal, and receiving the current from the other of the first output terminal and the second output terminal according to the first bit; and a voltage mode drive unit, coupled to the pair of differential output terminals, for providing voltages to the first output terminal and the second output terminal according to at least the second bit.
Abstract translation: 公开了一种用于接收输入数据并向终端元件产生输出信号的驱动电路，其中输入数据具有第一位和第二位，并且驱动电路包括：一对差分输出端，用于输出输出信号 ，其中所述一对差分输出端子具有第一输出端子和第二输出端子; 电流模式驱动单元，耦合到所述一对差分输出端子，用于从所述第一输出端子和所述第二输出端子之一输出电流，以及根据所述第一输出端子和所述第二输出端子中的另一个接收所述电流， 到第一位 以及耦合到所述一对差分输出端子的电压模式驱动单元，用于根据至少所述第二位向所述第一输出端子和所述第二输出端子提供电压。
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5.发明授权公开(公告)号：US09312846B2
公开(公告)日：2016-04-12
申请号：US14280701
申请日：2014-05-19
Applicant: MEDIATEK INC.
Inventor： Chien-Hua Wu , Yan-Bin Luo
CPC classification number: H03K17/16 , H03K19/018578 , H03K19/018585 , H04L25/00 , H04L25/0272 , H04L25/0282
Abstract: A driver circuit for receiving a data input and generating an output signal according to at least the data input is provided. The driver circuit includes a pair of differential output terminals, a current mode drive unit and a voltage mode drive unit. The pair of differential output terminals has a first output terminal and a second output terminal. The current mode drive unit is arranged for outputting a first reference current from one of the first and second output terminals and receiving the first reference current from the other of the first and the second output terminals according to the first data input. The voltage mode drive unit is arranged for coupling a first reference voltage to one of the first and the second output terminals and coupling a second reference voltage to the other of the first and the second output terminals according to the first data input.
Abstract translation: 提供了用于接收数据输入并至少根据数据输入产生输出信号的驱动电路。 驱动电路包括一对差分输出端子，电流模式驱动单元和电压模式驱动单元。 一对差分输出端子具有第一输出端子和第二输出端子。 电流模式驱动单元布置成从第一和第二输出端之一输出第一参考电流，并根据第一数据输入从第一和第二输出端中的另一个接收第一参考电流。 电压模式驱动单元用于将第一参考电压耦合到第一和第二输出端之一，并根据第一数据输入将第二参考电压耦合到第一和第二输出端中的另一个。
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Patent Agency Ranking
6.发明申请公开(公告)号：US20150022243A1
公开(公告)日：2015-01-22
申请号：US14280701
申请日：2014-05-19
Applicant: MEDIATEK INC.
Inventor： Chien-Hua Wu , Yan-Bin Luo
IPC: H03K17/16
CPC classification number: H03K17/16 , H03K19/018578 , H03K19/018585 , H04L25/00 , H04L25/0272 , H04L25/0282
Abstract: A driver circuit for receiving a data input and generating an output signal according to at least the data input is provided. The driver circuit includes a pair of differential output terminals, a current mode drive unit and a voltage mode drive unit. The pair of differential output terminals has a first output terminal and a second output terminal. The current mode drive unit is arranged for outputting a first reference current from one of the first and second output terminals and receiving the first reference current from the other of the first and the second output terminals according to the first data input. The voltage mode drive unit is arranged for coupling a first reference voltage to one of the first and the second output terminals and coupling a second reference voltage to the other of the first and the second output terminals according to the first data input.
Abstract translation: 提供了用于接收数据输入并至少根据数据输入产生输出信号的驱动电路。 驱动电路包括一对差分输出端子，电流模式驱动单元和电压模式驱动单元。 一对差分输出端子具有第一输出端子和第二输出端子。 电流模式驱动单元布置成从第一和第二输出端之一输出第一参考电流，并根据第一数据输入从第一和第二输出端中的另一个接收第一参考电流。 电压模式驱动单元用于将第一参考电压耦合到第一和第二输出端之一，并根据第一数据输入将第二参考电压耦合到第一和第二输出端中的另一个。
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公开(公告)号：US20160204768A1
公开(公告)日：2016-07-14
申请号：US14825149
申请日：2015-08-12
Applicant: Mediatek Inc.
Inventor： Yan-Bin Luo , Chien-Hua Wu , Chung-Shi Lin , Chih-Hsien Lin
CPC classification number: H03K3/012 , H03K19/017509 , H03K19/018528 , H03K19/018585 , H04L25/03076
Abstract: A driver circuit for receiving input data and generating an output signal to a termination element is provided, wherein the input data has a first bit and second bit, and the driver circuit includes: a pair of differential output terminals for outputting the output signal, wherein the pair of differential output terminals has a first output terminal and a second output terminal; at least one current mode drive unit, coupled to the pair of differential output terminals, for outputting a current from one of the first output terminal and the second output terminal, and receiving the current from the other of the first output terminal and the second output terminal according to the first bit; and at least one voltage mode drive unit, coupled to the pair of differential output terminals, for providing voltages to the first output terminal and the second output terminal according to the second bit.
Abstract translation: 提供了一种用于接收输入数据并向终端元件产生输出信号的驱动电路，其中输入数据具有第一位和第二位，并且驱动电路包括：一对差分输出端，用于输出输出信号，其中 一对差分输出端子具有第一输出端子和第二输出端子; 耦合到所述一对差分输出端子的至少一个电流模式驱动单元，用于从所述第一输出端子和所述第二输出端子之一输出电流，以及从所述第一输出端子和所述第二输出端子中的另一个接收电流 终端根据第一位; 以及耦合到所述一对差分输出端子的至少一个电压模式驱动单元，用于根据所述第二位向所述第一输出端子和所述第二输出端子提供电压。
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公开(公告)号：US10594311B2
公开(公告)日：2020-03-17
申请号：US15464375
申请日：2017-03-21
Applicant: MEDIATEK Inc.
Inventor： Chien-Hua Wu
IPC: H03B1/00 , H03K3/00 , H03K17/04 , H03K19/0185
Abstract: A driver circuit is provided. The driver circuit includes a differential driver, a first feedback passive circuit and a second feedback passive circuit. The differential driver includes a first half circuit and a second half circuit. The first half circuit has a first input point and a first output point. The second half circuit has a second input point and a second output point. The first feedback passive circuit is coupled to the second input point and the first output point. The second feedback passive circuit is coupled to the first input point and the second output point.
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公开(公告)号：US20180131360A1
公开(公告)日：2018-05-10
申请号：US15464375
申请日：2017-03-21
Applicant: MEDIATEK Inc.
Inventor： Chien-Hua Wu
IPC: H03K17/04
CPC classification number: H03K17/04 , H03K19/0185
Abstract: A driver circuit is provided. The driver circuit includes a differential driver, a first feedback passive circuit and a second feedback passive circuit. The differential driver includes a first half circuit and a second half circuit. The first half circuit has a first input point and a first output point. The second half circuit has a second input point and a second output point. The first feedback passive circuit is coupled to the second input point and the first output point. The second feedback passive circuit is coupled to the first input point and the second output point.
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公开(公告)号：US09871539B2
公开(公告)日：2018-01-16
申请号：US15069880
申请日：2016-03-14
Applicant: MEDIATEK INC.
Inventor： Chien-Hua Wu , Yan-Bin Luo
IPC: H03B1/04 , H04L25/00 , H04B1/04 , H03K19/0185 , H04L25/02 , H03K19/0175
CPC classification number: H04B1/04 , H03K19/017545 , H03K19/018578 , H03K19/018585 , H04L25/00 , H04L25/0272
Abstract: A driver circuit for receiving a data input and generating an output signal to a termination element according to at least the first data input is provided. The driver circuit includes a first output terminal, a current mode drive unit and a voltage mode drive unit. The current mode drive unit is arranged for selectively outputting a first reference current from the first output terminal to the termination element according to the first data input, and selectively receiving the first reference current through the first output terminal according to the first data input. The voltage mode drive unit is arranged for coupling one of a first reference voltage and a second reference voltage different from the second reference voltage to the first output terminal according to the first data input.
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