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公开(公告)号：US20230134814A1
公开(公告)日：2023-05-04
申请号：US18147342
申请日：2022-12-28
发明人： Aaron S. Yip , Kunal R. Parekh , Akira Goda
IPC分类号： H01L25/18 , H01L25/065 , H01L23/00 , H01L25/00
摘要： A microelectronic device comprises a first die comprising a memory array region comprising a stack structure comprising vertically alternating conductive structures and insulative structures, and vertically extending strings of memory cells within the stack structure. The first die further comprises first control logic region comprising a first control logic devices including at least a word line driver. The microelectronic device further comprise a second die attached to the first die, the second die comprising a second control logic region comprising second control logic devices including at least one page buffer device configured to effectuate a portion of control operations of the vertically extending string of memory cells. Related microelectronic devices, electronic systems, and methods are also described.
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公开(公告)号：US11545456B2
公开(公告)日：2023-01-03
申请号：US16992566
申请日：2020-08-13
发明人： Akira Goda , Kunal R. Parekh , Aaron S. Yip
IPC分类号： H01L23/00 , H01L25/18 , H01L27/11565 , H01L27/11573 , H01L27/11519 , H01L27/11556 , H01L27/11526 , H01L27/11582
摘要： A microelectronic device comprises a first die and a second die attached to the first die. The first die comprises a memory array region comprising a stack structure comprising vertically alternating conductive structures and insulative structures, vertically extending strings of memory cells within the stack structure, and first bond pad structures vertically neighboring the vertically extending strings of memory cells. The second die comprises a control logic region comprising control logic devices configured to effectuate at least a portion of control operations for the vertically extending string of memory cells, second bond pad structures in electrical communication with the first bond pad structures, and signal routing structures located at an interface between the first die and the second die. Related microelectronic devices, electronic systems, and methods are also described.
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公开(公告)号：US20210358554A1
公开(公告)日：2021-11-18
申请号：US17443841
申请日：2021-07-28
发明人： Aaron S. Yip
摘要： Apparatus might include a controller configured to cause the apparatus to program a plurality of memory cells from a first data state to a second data state higher than the first data state, determine a respective first voltage level of a control gate voltage deemed to cause each memory cell of a first and second subset of memory cells of the plurality of memory cells to reach the second data state, determine a respective second voltage level of a control gate voltage deemed sufficient to cause each memory cell of the first subset of memory cells to reach a third data state higher than the second data state, and determine a respective second voltage level of a control gate voltage deemed sufficient to cause each memory cell of the second subset of memory cells to reach a fourth data state higher than the third data state.
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公开(公告)号：US11094379B1
公开(公告)日：2021-08-17
申请号：US16835664
申请日：2020-03-31
发明人： Aaron S. Yip
摘要： Methods, as well as apparatus configured to perform similar methods, might include programming a plurality of memory cells to a particular data state of a plurality of data states, and, for each memory cell of the plurality of memory cells whose target data state is higher than the particular data state, determining a respective indication of a programming voltage level deemed sufficient to program that memory cell to a respective target threshold voltage corresponding to its respective target data state, and further programming that memory cell using a programming voltage level of a plurality of programming voltage levels corresponding to the respective indication of the programming voltage level deemed sufficient to program that memory cell to the respective target threshold voltage corresponding to its respective target data state.
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5.发明授权公开(公告)号：US11043272B2
公开(公告)日：2021-06-22
申请号：US16516791
申请日：2019-07-19
发明人： Aaron S. Yip
摘要： Methods of operating a memory include applying a programming pulse having a particular voltage level to a selected access line connected to a plurality of memory cells selected for programming during a programming operation, concurrently enabling for programming each memory cell of the plurality of memory cells selected for programming while applying the programming pulse, applying a subsequent programming pulse having a plurality of different voltage levels to the selected access line, and, for each group of memory cells of a plurality of groups of memory cells of the plurality of memory cells selected for programming, enabling that group of memory cells for programming while the subsequent programming pulse has a corresponding voltage level of the plurality of different voltage levels.
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公开(公告)号：US20190287623A1
公开(公告)日：2019-09-19
申请号：US16427587
申请日：2019-05-31
发明人： Aaron S. Yip
摘要： Memories having a controller configured to apply a first voltage level to channel regions of memory cells of an array of memory cells coupled to a plurality of access lines; apply a second voltage level, lower than the first voltage level, to a first access line; apply a third voltage level, lower than the second voltage level, to a second access line while applying the second voltage level to the first access line and while applying the first voltage level to the channel regions of the memory cells; and increase the voltage level applied to the second access line to the second voltage level and decrease the voltage level applied to the first access line to a fourth voltage level, lower than the second voltage level and different than the third voltage level, while applying the first voltage level to the channel regions of the memory cells.
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公开(公告)号：US09875802B2
公开(公告)日：2018-01-23
申请号：US15342255
申请日：2016-11-03
发明人： Benjamin Louie , Ali Mohammadzadeh , Aaron S. Yip
IPC分类号： G11C5/14 , G11C16/24 , G11C16/04 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/26
摘要： Memory devices are configured to store a number of access line biasing patterns to be applied during a memory device operation performed on a particular row of memory cells in the memory device. Memory devices are further configured to support modification of the stored bias patterns, providing flexibility in biasing access lines through changes to the bias patterns stored in the memory device. Methods and devices further facilitate performing memory device operations under multiple biasing conditions to evaluate and characterize the memory device by adjustment of the stored bias patterns without requiring an associated hardware change to the memory device.
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公开(公告)号：US09218884B2
公开(公告)日：2015-12-22
申请号：US14153590
申请日：2014-01-13
发明人： Benjamin Louie , Ali Mohammadzadeh , Aaron S. Yip
摘要： Memory devices and methods are disclosed, such as devices configured to store a number of access line biasing patterns to be applied during a memory device operation performed on a particular row of memory cells in the memory device. Memory devices are further configured to support modification of the stored bias patterns, providing flexibility in biasing access lines through changes to the bias patterns stored in the memory device. Methods and devices further facilitate performing memory device operations under multiple biasing conditions to evaluate and characterize the memory device by adjustment of the stored bias patterns without requiring an associated hardware change to the memory device.
摘要翻译： 公开了存储器件和方法，诸如被配置为存储在对存储器件中的特定行存储器单元执行的存储器件操作期间要施加的多个访问线偏置模式的器件。 存储器设备被进一步配置为支持所存储的偏置图案的修改，通过对存储在存储器件中的偏置图案的改变来偏置访问线路提供灵活性。 方法和设备进一步便于在多个偏置条件下执行存储器件操作，以通过调整存储的偏压图案来评估和表征存储器件，而不需要对存储器件的相关联的硬件改变。
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公开(公告)号：US20240315028A1
公开(公告)日：2024-09-19
申请号：US18604200
申请日：2024-03-13
发明人： Paolo Tessariol , Aaron S. Yip , Giovanni Mazzone , Matthew King
CPC分类号： H10B43/27 , G11C16/0483 , G11C16/10 , H10B41/27
摘要： A system for manufacturing a memory device forms a memory array comprising a plurality of memory cells arranged in a plurality of memory strings along a plurality of memory array pillars, wherein respective subsets of the memory array pillars correspond to respective sub-blocks of a block of the memory array, and forms a plurality of deintegrated source segments adjacent to the memory array, wherein the source segments of the plurality of deintegrated source segments are associated with respective sub-blocks and are physically segregated from one another.
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10.发明公开公开(公告)号：US20240071501A1
公开(公告)日：2024-02-29
申请号：US18364397
申请日：2023-08-02
发明人： Lifang Xu , Umberto Maria Meotto , Aaron S. Yip
IPC分类号： G11C16/04 , H01L23/528 , H10B41/10 , H10B41/27 , H10B41/35 , H10B43/10 , H10B43/27 , H10B43/35
CPC分类号： G11C16/0483 , H01L23/5283 , H10B41/10 , H10B41/27 , H10B41/35 , H10B43/10 , H10B43/27 , H10B43/35
摘要： Microelectronic devices include a stack having a vertically alternating sequence of insulative and conductive structures arranged in tiers. Slit structures extend through the stack, dividing the stack into blocks. A first series of stadiums—within the stack of a first block of a pair of the blocks—includes at least one stadium having multiple parallel sets of staircases. A second series of stadiums—within the stack of a second block of the pair of blocks—includes at least one additional stadium having additional multiple parallel sets of staircases that are mirrored, across one of the slit structures, to the multiple parallel sets of staircases of the first series. In methods of fabrication, common mask openings are used to form the mirrored staircase profiles once stadiums are already at substantially their final depths in the stack structure. Electronic systems are also disclosed.
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