公开(公告)号：US20200251347A1

公开(公告)日：2020-08-06

申请号：US16854283

申请日：2020-04-21

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Gordon A. Haller ,  Tom J. John ,  Anish A. Khandekar ,  Christopher Larsen ,  Kunal Shrotri

IPC: H01L21/311 ,  H01L27/11582 ,  H01L21/02 ,  H01L27/11556

Abstract: A method used in forming an array of elevationally-extending strings of memory cells comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. The stack comprises an etch-stop tier between a first tier and a second tier of the stack. The etch-stop tier is of different composition from those of the insulative tiers and the wordline tiers. Etching is conducted into the insulative tiers and the wordline tiers that are above the etch-stop tier to the etch-stop tier to form channel openings that have individual bases comprising the etch-stop tier. The etch-stop tier is penetrated through to extend individual of the channel openings there-through. After extending the individual channel openings through the etch-stop tier, etching is conducted into and through the insulative tiers and the wordline tiers that are below the etch-stop tier to extend the individual channel openings deeper into the stack below the etch-stop tier. Transistor channel material is formed in the individual channel openings elevationally along the etch-stop tier and along the insulative tiers and the wordline tiers that are above and below the etch-stop tier. Arrays independent of method are disclosed.

公开(公告)号：US20210202515A1

公开(公告)日：2021-07-01

申请号：US16728723

申请日：2019-12-27

Applicant: Micron Technology, Inc.

Inventor： Anilkumar Chandolu ,  S.M. Istiaque Hossain ,  Darwin A. Clampitt ,  Arun Kumar Dhayalan ,  Kevin R. Gast ,  Christopher Larsen ,  Prakash Rau Mokhna Rau ,  Shashank Saraf

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11565 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers comprising memory-block regions having channel-material strings therein. Conductor-material contacts are directly against the channel material of individual of the channel-material strings. First insulator material is formed directly above the conductor-material contacts. The first insulator material comprises at least one of (a) and (b), where (a): silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus, and (b): silicon carbide. Second insulator material is formed directly above the first insulator material and the conductor-material contacts. The second insulator material is devoid of each of the (a) and (b). Third insulator material is formed directly above the second insulator material, the first insulator material, and the conductor-material contacts. The third insulator material comprises at least one of the (a) and (b). At least one horizontally-elongated isolation structure is formed in the first and second insulator materials and in a top part of the stack in individual of the memory-block regions. Additional methods, including structure independent of method, are disclosed.

公开(公告)号：US10665469B2

公开(公告)日：2020-05-26

申请号：US16128109

申请日：2018-09-11

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Gordon A. Haller ,  Tom J. John ,  Anish A. Khandekar ,  Christopher Larsen ,  Kunal Shrotri

IPC: H01L27/115 ,  H01L21/311 ,  H01L27/11556 ,  H01L21/02 ,  H01L27/11582

Abstract: A method used in forming an array of elevationally-extending strings of memory cells comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. The stack comprises an etch-stop tier between a first tier and a second tier of the stack. The etch-stop tier is of different composition from those of the insulative tiers and the wordline tiers. Etching is conducted into the insulative tiers and the wordline tiers that are above the etch-stop tier to the etch-stop tier to form channel openings that have individual bases comprising the etch-stop tier. The etch-stop tier is penetrated through to extend individual of the channel openings there-through. After extending the individual channel openings through the etch-stop tier, etching is conducted into and through the insulative tiers and the wordline tiers that are below the etch-stop tier to extend the individual channel openings deeper into the stack below the etch-stop tier. Transistor channel material is formed in the individual channel openings elevationally along the etch-stop tier and along the insulative tiers and the wordline tiers that are above and below the etch-stop tier. Arrays independent of method are disclosed.

公开(公告)号：US10658382B2

公开(公告)日：2020-05-19

申请号：US16386544

申请日：2019-04-17

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  David Daycock ,  Yushi Hu ,  Christopher Larsen ,  Dimitrios Pavlopoulos

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L21/225 ,  H01L27/11556 ,  H01L29/788 ,  H01L27/11568 ,  H01L27/11565 ,  H01L27/11519 ,  H01L23/532 ,  H01L23/528

Abstract: An elevationally-extending string of memory cells comprises an upper stack elevationally over a lower stack. The upper and lower stacks individually comprise vertically-alternating tiers comprising control gate material of individual charge storage field effect transistors vertically alternating with insulating material. An upper stack channel pillar extends through multiple of the vertically-alternating tiers in the upper stack and a lower stack channel pillar extends through multiple of the vertically-alternating tiers in the lower stack. Tunnel insulator, charge storage material, and control gate blocking insulator is laterally between the respective upper and lower stack channel pillars and the control gate material. A conductive interconnect comprising conductively-doped semiconductor material is elevationally between and electrically couples the upper and lower stack channel pillars together. The conductively-doped semiconductor material comprises a first conductivity-producing dopant. The conductive interconnect comprises a lower half thereof having a conductive region comprising at least one of (a) conductive material below the conductively-doped semiconductor material, or (b) a second non-p-type dopant within the conductively-doped semiconductor material that is different from the first dopant, the second dopant being present at an atomic concentration within the semiconductor material of at least 0.1%. Other embodiments, including method, are disclosed.

公开(公告)号：US20190244972A1

公开(公告)日：2019-08-08

申请号：US16386544

申请日：2019-04-17

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  David Daycock ,  Yushi Hu ,  Christopher Larsen ,  Dimitrios Pavlopoulos

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L21/225 ,  H01L27/11556 ,  H01L29/788 ,  H01L27/11568 ,  H01L27/11565 ,  H01L27/11519 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L27/11582 ,  H01L21/225 ,  H01L23/528 ,  H01L23/53266 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/7883

Abstract: An elevationally-extending string of memory cells comprises an upper stack elevationally over a lower stack. The upper and lower stacks individually comprise vertically-alternating tiers comprising control gate material of individual charge storage field effect transistors vertically alternating with insulating material. An upper stack channel pillar extends through multiple of the vertically-alternating tiers in the upper stack and a lower stack channel pillar extends through multiple of the vertically-alternating tiers in the lower stack. Tunnel insulator, charge storage material, and control gate blocking insulator is laterally between the respective upper and lower stack channel pillars and the control gate material. A conductive interconnect comprising conductively-doped semiconductor material is elevationally between and electrically couples the upper and lower stack channel pillars together. The conductively-doped semiconductor material comprises a first conductivity-producing dopant. The conductive interconnect comprises a lower half thereof having a conductive region comprising at least one of (a) conductive material below the conductively-doped semiconductor material, or (b) a second non-p-type dopant within the conductively-doped semiconductor material that is different from the first dopant, the second dopant being present at an atomic concentration within the semiconductor material of at least 0.1%. Other embodiments, including method, are disclosed.

公开(公告)号：US10283520B2

公开(公告)日：2019-05-07

申请号：US15208206

申请日：2016-07-12

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  David Daycock ,  Yushi Hu ,  Christopher Larsen ,  Dimitrios Pavlopoulos

IPC: H01L29/788 ,  H01L21/225 ,  H01L23/532 ,  H01L23/528 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11524

Abstract: An elevationally-extending string of memory cells comprises an upper stack elevationally over a lower stack. The upper and lower stacks individually comprise vertically-alternating tiers comprising control gate material of individual charge storage field effect transistors vertically alternating with insulating material. An upper stack channel pillar extends through multiple of the vertically-alternating tiers in the upper stack and a lower stack channel pillar extends through multiple of the vertically-alternating tiers in the lower stack. Tunnel insulator, charge storage material, and control gate blocking insulator is laterally between the respective upper and lower stack channel pillars and the control gate material. A conductive interconnect comprising conductively-doped semiconductor material is elevationally between and electrically couples the upper and lower stack channel pillars together. The conductively-doped semiconductor material comprises a first conductivity-producing dopant. The conductive interconnect comprises a lower half thereof having a conductive region comprising at least one of (a) conductive material below the conductively-doped semiconductor material, or (b) a second non-p-type dopant within the conductively-doped semiconductor material that is different from the first dopant, the second dopant being present at an atomic concentration within the semiconductor material of at least 0.1%. Other embodiments, including method, are disclosed.

公开(公告)号：US20180323212A1

公开(公告)日：2018-11-08

申请号：US16031919

申请日：2018-07-10

Applicant: Micron Technology, Inc.

Inventor： David Daycock ,  Richard J. Hill ,  Christopher Larsen ,  Woohee Kim ,  Justin B. Dorhout ,  Brett D. Lowe ,  John D. Hopkins ,  Qian Tao ,  Barbara L. Casey

IPC: H01L27/11582 ,  H01L29/423 ,  H01L21/28 ,  H01L27/1157 ,  H01L29/10

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L29/1037 ,  H01L29/4234 ,  H01L29/7926

Abstract: Some embodiments include a memory array which has a vertical stack of alternating insulative levels and wordline levels. The wordline levels have terminal ends corresponding to control gate regions. Charge-trapping material is along the control gate regions of the wordline levels and not along the insulative levels. The charge-trapping material is spaced from the control gate regions by charge-blocking material. Channel material extends vertically along the stack and is laterally spaced from the charge-trapping material by dielectric material. Some embodiments include methods of forming NAND memory arrays.

公开(公告)号：US10083981B2

公开(公告)日：2018-09-25

申请号：US15422335

申请日：2017-02-01

Applicant: Micron Technology, Inc.

Inventor： David Daycock ,  Richard J. Hill ,  Christopher Larsen ,  Woohee Kim ,  Justin B. Dorhout ,  Brett D. Lowe ,  John D. Hopkins ,  Qian Tao ,  Barbara L. Casey

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L29/423 ,  H01L21/28 ,  H01L29/10

Abstract: Some embodiments include a memory array which has a vertical stack of alternating insulative levels and wordline levels. The wordline levels have terminal ends corresponding to control gate regions. Charge-trapping material is along the control gate regions of the wordline levels and not along the insulative levels. The charge-trapping material is spaced from the control gate regions by charge-blocking material. Channel material extends vertically along the stack and is laterally spaced from the charge-trapping material by dielectric material. Some embodiments include methods of forming NAND memory arrays.

公开(公告)号：US20180019255A1

公开(公告)日：2018-01-18

申请号：US15208206

申请日：2016-07-12

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  David Daycock ,  Yushi Hu ,  Christopher Larsen ,  Dimitrios Pavlopoulos

IPC: H01L29/788 ,  H01L23/532 ,  H01L23/528 ,  H01L21/225

CPC classification number: H01L27/11582 ,  H01L21/225 ,  H01L23/528 ,  H01L23/53266 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/7883

Abstract: An elevationally-extending string of memory cells comprises an upper stack elevationally over a lower stack. The upper and lower stacks individually comprise vertically-alternating tiers comprising control gate material of individual charge storage field effect transistors vertically alternating with insulating material. An upper stack channel pillar extends through multiple of the vertically-alternating tiers in the upper stack and a lower stack channel pillar extends through multiple of the vertically-alternating tiers in the lower stack. Tunnel insulator, charge storage material, and control gate blocking insulator is laterally between the respective upper and lower stack channel pillars and the control gate material. A conductive interconnect comprising conductively-doped semiconductor material is elevationally between and electrically couples the upper and lower stack channel pillars together. The conductively-doped semiconductor material comprises a first conductivity-producing dopant. The conductive interconnect comprises a lower half thereof having a conductive region comprising at least one of (a) conductive material below the conductively-doped semiconductor material, or (b) a second non-p-type dopant within the conductively-doped semiconductor material that is different from the first dopant, the second dopant being present at an atomic concentration within the semiconductor material of at least 0.1%. Other embodiments, including method, are disclosed.

公开(公告)号：US11600494B2

公开(公告)日：2023-03-07

申请号：US17318470

申请日：2021-05-12

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Gordon A. Haller ,  Tom J. John ,  Anish A. Khandekar ,  Christopher Larsen ,  Kunal Shrotri

IPC: H01L21/311 ,  H01L27/11556 ,  H01L21/02 ,  H01L27/11582

Abstract: A method used in forming an array of elevationally-extending strings of memory cells comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. The stack comprises an etch-stop tier between a first tier and a second tier of the stack. The etch-stop tier is of different composition from those of the insulative tiers and the wordline tiers. Etching is conducted into the insulative tiers and the wordline tiers that are above the etch-stop tier to the etch-stop tier to form channel openings that have individual bases comprising the etch-stop tier. The etch-stop tier is penetrated through to extend individual of the channel openings there-through. After extending the individual channel openings through the etch-stop tier, etching is conducted into and through the insulative tiers and the wordline tiers that are below the etch-stop tier to extend the individual channel openings deeper into the stack below the etch-stop tier. Transistor channel material is formed in the individual channel openings elevationally along the etch-stop tier and along the insulative tiers and the wordline tiers that are above and below the etch-stop tier. Arrays independent of method are disclosed.