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公开(公告)号：US20250140324A1
公开(公告)日：2025-05-01
申请号：US19010407
申请日：2025-01-06
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Giovanni Maria Paolucci , Paolo Tessariol , Emilio Camerlenghi , Gianpietro Carnevale , Augusto Benvenuti
Abstract: Memories having a controller configured to increase a voltage level applied to a data line and decrease a voltage level applied to a control gate of a transistor connected between the data line and a string of series-connected memory cells during a first period of time, increase the voltage level applied to the data line and increase the voltage level applied to the control gate of the transistor at a same rate in response to an end of the first period of time, and ceasing increasing the voltage level applied to the data line and ceasing increasing the voltage level applied to the control gate of the transistor in response to the voltage level applied to the data line reaching a predetermined voltage level.
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公开(公告)号：US11514987B2
公开(公告)日：2022-11-29
申请号：US17228807
申请日：2021-04-13
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Giovanni Maria Paolucci , Paolo Tessariol , Emilio Camerlenghi , Gianpietro Carnevale , Augusto Benvenuti
Abstract: Methods of operating a memory, and memory configured to perform similar methods, might include applying a positive first voltage level to a first node selectively connected to a string of series-connected memory cells while applying a negative second voltage level to a control gate of a transistor connected between the first node and the string of series-connected memory cells, and increasing the voltage level applied to the first node to a third voltage level while increasing the voltage level applied to the control gate of the transistor to a fourth voltage level lower than the third voltage level and higher than the first voltage level.
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公开(公告)号：US20250117158A1
公开(公告)日：2025-04-10
申请号：US18984322
申请日：2024-12-17
Applicant: Micron Technology, Inc.
Inventor： Giovanni Maria Paolucci
IPC: G06F3/06
Abstract: An example memory device includes a memory array and processing logic to perform operations including: identifying, among a plurality of memory cells of the memory array, a target memory cell and a set of memory cells adjacent to the target memory cell, such that each memory cell of the set of memory cells is characterized by a respective memory cell state; determining, for each memory cell state, a respective interference value reflecting memory cell-to-memory cell interference; assigning, based on the respective interference value, each memory cell state to a respective bin of a set of state information bins; and determining a set of read level offsets for reading the target memory cell, such that each read level offset of the set of read level offsets is associated with a respective bin of the set of state information bins.
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公开(公告)号：US20240087651A1
公开(公告)日：2024-03-14
申请号：US17941831
申请日：2022-09-09
Applicant: Micron Technology, Inc.
Inventor： Kishore Kumar Muchherla , Huai-Yuan Tseng , Akira Goda , Dung V. Nguyen , Giovanni Maria Paolucci , James Fitzpatrick , Eric N. Lee , Dave Scott Ebsen , Tomoharu Tanaka
CPC classification number: G11C16/102 , G11C16/26 , G11C16/32
Abstract: Exemplary methods, apparatuses, and systems include an adaptive pre-read manager for controlling pre-reads of the memory device. The adaptive pre-read manager receives a first set of data bits for programming to memory. The adaptive pre-read manager performing a first pass of programming including a first subset of data bits from the set of data bits. The adaptive pre-read manager compares a set of threshold operating differences to a set of differences between multiple operating conditions during the first pass of programming and current operating conditions. The adaptive pre-read manager performs an internal pre-read of the programmed first subset of data bits. The adaptive pre-read manager performs a second pass of programming using the internal pre-read and a second subset of data bits from the first set of data bits.
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公开(公告)号：US20230075673A1
公开(公告)日：2023-03-09
申请号：US17987779
申请日：2022-11-15
Applicant: Micron Technology, Inc.
Inventor： Ramanathan Gandhi , Augusto Benvenuti , Giovanni Maria Paolucci
IPC: H01L29/51
Abstract: A transistor comprises a channel region having a frontside and a backside. A gate is adjacent the frontside of the channel region with a gate insulator being between the gate and the channel region. Insulating material having net negative charge is adjacent the backside of the channel region. The insulating material comprises at least one of AlxFy, HfAlxFy, AlOxNy, and HfAlxOyNz, where “x”, “y”, and “z” are each greater than zero. Other embodiments and aspects are disclosed.
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Patent Agency Ranking
公开(公告)号：US12210769B2
公开(公告)日：2025-01-28
申请号：US18228065
申请日：2023-07-31
Applicant: Micron Technology, Inc.
Inventor： Giovanni Maria Paolucci
IPC: G06F3/06
Abstract: A memory device includes a memory array and control logic to perform operations including identifying a target cell and a set of cells adjacent to the target cell. Each cell of the set of cells is associated with a respective adjacent cell state. The operations further include determining, for each adjacent cell state, a respective interference value, assigning, based on the respective interference value, each adjacent cell state to a respective bin of a set of state information bins, and in response to determining that each bin of the set of state information bins has at least one adjacent cell state assigned to it, and determining a set of read level offsets for reading the target cell. Each read level offset of the set of read level offsets is associated with a respective bin of the set of state information bins.
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公开(公告)号：US20240071510A1
公开(公告)日：2024-02-29
申请号：US17899409
申请日：2022-08-30
Applicant: Micron Technology, Inc.
Inventor： Kishore Kumar Muchherla , Huai-Yuan Tseng , Giovanni Maria Paolucci , Dave Scott Ebsen , James Fitzpatrick , Akira Goda , Jeffrey S. McNeil , Umberto Siciliani , Daniel J. Hubbard , Walter Di Francesco , Michele Incarnati
CPC classification number: G11C16/102 , G11C16/08 , G11C16/3404
Abstract: Exemplary methods, apparatuses, and systems including a programming manager for controlling writing data bits to a memory device. The programming manager receives a first set of data bits for programming to memory. The programming manager writes a first subset of data bits to a first wordline during a first pass of programming. The programming manager writes a second subset of data bits of the first set of data bits to a buffer. The programming manager receives a second set of data bits for programming. The programming manager writes the second subset of data bits of the first set of data bits to the first wordline during a second pass of programming to increase a bit density of memory cells in the first wordline in response to receiving the second set of data bits.
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公开(公告)号：US20240069749A1
公开(公告)日：2024-02-29
申请号：US18236087
申请日：2023-08-21
Applicant: Micron Technology, Inc.
Inventor： Augusto Benvenuti , Giovanni Maria Paolucci , Alessio Urbani , Gianpietro Carnevale , Aurelio Giancarlo Mauri
IPC: G06F3/06
CPC classification number: G06F3/0619 , G06F3/0655 , G06F3/0679
Abstract: A memory access operation is initiated to read a set of target memory cells of a target wordline of the memory device. During the memory access operation, a read voltage level is caused to be applied to the target wordline. During the memory access operation, a first pass through voltage level is caused to be applied to a first wordline adjacent to the target wordline. During the memory access operation, a second pass through voltage is caused to be applied to a second wordline adjacent to the target wordline, wherein the first pass through voltage level is less than the second pass through voltage level.
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公开(公告)号：US11538919B2
公开(公告)日：2022-12-27
申请号：US17182808
申请日：2021-02-23
Applicant: Micron Technology, Inc.
Inventor： Ramanathan Gandhi , Augusto Benvenuti , Giovanni Maria Paolucci
IPC: H01L29/51
Abstract: A transistor comprises a channel region having a frontside and a backside. A gate is adjacent the frontside of the channel region with a gate insulator being between the gate and the channel region. Insulating material having net negative charge is adjacent the backside of the channel region. The insulating material comprises at least one of AlxFy, HfAlxFy, AlOxNy, and HfAlxOyNz, where “x”, “y”, and “z” are each greater than zero. Other embodiments and aspects are disclosed.
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公开(公告)号：US11011236B2
公开(公告)日：2021-05-18
申请号：US16555050
申请日：2019-08-29
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Giovanni Maria Paolucci , Paolo Tessariol , Emilio Camerlenghi , Gianpietro Carnevale , Augusto Benvenuti
Abstract: Methods of operating a memory, and memory configured to perform similar methods, might include applying a positive first voltage level to a first node selectively connected to a string of series-connected memory cells while applying a negative second voltage level to a control gate of a transistor connected between the first node and the string of series-connected memory cells, and increasing the voltage level applied to the first node to a third voltage level while increasing the voltage level applied to the control gate of the transistor to a fourth voltage level lower than the third voltage level and higher than the first voltage level.
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