公开(公告)号：US20240362114A1

公开(公告)日：2024-10-31

申请号：US18607152

申请日：2024-03-15

Applicant: Micron Technology, Inc.

Inventor： Jaeil Kim ,  Donald M. Morgan ,  Alan J. Wilson

IPC: G06F11/10

CPC classification number: G06F11/1068 ,  G06F11/1016

Abstract: A system for providing memory management holding latch placement and control signal generation is disclosed. The system performs memory management operations on a memory device to reduce memory cell wear and tear and to balance use of the memory cells of the memory device. The system separates memory management read operations from memory management write operations by utilizing a holding register that stores data from a source memory cell prior to transfer to a target memory cell. When a memory management read operation is initiated, data and error correction parity bits from the source memory cell are provided to a circuit including the holding register. The data and parity bits are analyzed for errors and the errors are corrected prior to storing the data and parity bits into the holding register. The data and associated parity bits are then transferred from the holding register to the target memory cell.

公开(公告)号：US11740795B2

公开(公告)日：2023-08-29

申请号：US17721160

申请日：2022-04-14

Applicant: Micron Technology, Inc.

Inventor： Suryanarayana B. Tatapudi ,  John David Porter ,  Jaeil Kim ,  Mijo Kim

IPC: G06F3/06 ,  G06F13/16 ,  G11C7/10

CPC classification number: G06F3/061 ,  G06F3/0655 ,  G06F3/0676 ,  G06F3/0679 ,  G06F13/1668 ,  G11C7/10 ,  G06F2213/16

Abstract: Techniques for configurable link interfaces for a memory device are described. In some examples, memory devices may require periodic link training to support data transfer with a host device at relatively fast rates. However, in some managed memory applications, memory dies of a memory device may have integrated controllers that do not support such link training, and accordingly may not support some clock rates or data rates. To support data transfers between a host device and a memory device at relatively fast clock rates or data rates without link training, a memory die may be fabricated with a configurable link interface that can support different mappings between components and operation according to different clock rates or data rates. In some examples, a memory die may be fabricated in a manner that supports configurable mappings between an array and a data channel interface that are operable according to different multiplexing and serialization.

公开(公告)号：US20220011934A1

公开(公告)日：2022-01-13

申请号：US16925773

申请日：2020-07-10

Applicant: Micron Technology, Inc.

Inventor： Suryanarayana B. Tatapudi ,  John David Porter ,  Jaeil Kim ,  Mijo Kim

IPC: G06F3/06 ,  G06F13/16

Abstract: Techniques for configurable link interfaces for a memory device are described. In some examples, memory devices may require periodic link training to support data transfer with a host device at relatively fast rates. However, in some managed memory applications, memory dies of a memory device may have integrated controllers that do not support such link training, and accordingly may not support some clock rates or data rates. To support data transfers between a host device and a memory device at relatively fast clock rates or data rates without link training, a memory die may be fabricated with a configurable link interface that can support different mappings between components and operation according to different clock rates or data rates. In some examples, a memory die may be fabricated in a manner that supports configurable mappings between an array and a data channel interface that are operable according to different multiplexing and serialization.

公开(公告)号：US20240232028A1

公开(公告)日：2024-07-11

申请号：US18403198

申请日：2024-01-03

Applicant: Micron Technology, Inc.

Inventor： Jaeil Kim ,  Simon J. Lovett

IPC: G06F11/16 ,  G06F3/06

CPC classification number: G06F11/1612 ,  G06F3/0619 ,  G06F3/0658 ,  G06F3/0673 ,  G06F2201/805

Abstract: A memory device can include a bank of memory cells. The bank of memory cells can include multiple groups of columns of memory cells. The memory device can include controller circuitry to provide information pertaining to a column repair redundancy swap for repairing a selected group of the plurality of groups at row address strobe (RAS) time. Upon detection of an error condition in at least one group of columns of memory cells, the controller circuitry can implement the column repair redundancy swap on the corresponding group.

公开(公告)号：US20220308757A1

公开(公告)日：2022-09-29

申请号：US17721160

申请日：2022-04-14

Applicant: Micron Technology, Inc.

Inventor： Suryanarayana B. Tatapudi ,  John David Porter ,  Jaeil Kim ,  Mijo Kim

IPC: G06F3/06 ,  G06F13/16 ,  G11C7/10

Abstract: Techniques for configurable link interfaces for a memory device are described. In some examples, memory devices may require periodic link training to support data transfer with a host device at relatively fast rates. However, in some managed memory applications, memory dies of a memory device may have integrated controllers that do not support such link training, and accordingly may not support some clock rates or data rates. To support data transfers between a host device and a memory device at relatively fast clock rates or data rates without link training, a memory die may be fabricated with a configurable link interface that can support different mappings between components and operation according to different clock rates or data rates. In some examples, a memory die may be fabricated in a manner that supports configurable mappings between an array and a data channel interface that are operable according to different multiplexing and serialization.

公开(公告)号：US11307771B2

公开(公告)日：2022-04-19

申请号：US16925773

申请日：2020-07-10

Applicant: Micron Technology, Inc.

Inventor： Suryanarayana B. Tatapudi ,  John David Porter ,  Jaeil Kim ,  Mijo Kim

IPC: G06F3/06 ,  G06F13/16 ,  G11C7/10

Abstract: Techniques for configurable link interfaces for a memory device are described. In some examples, memory devices may require periodic link training to support data transfer with a host device at relatively fast rates. However, in some managed memory applications, memory dies of a memory device may have integrated controllers that do not support such link training, and accordingly may not support some clock rates or data rates. To support data transfers between a host device and a memory device at relatively fast clock rates or data rates without link training, a memory die may be fabricated with a configurable link interface that can support different mappings between components and operation according to different clock rates or data rates. In some examples, a memory die may be fabricated in a manner that supports configurable mappings between an array and a data channel interface that are operable according to different multiplexing and serialization.

公开(公告)号：US11651814B2

公开(公告)日：2023-05-16

申请号：US17511489

申请日：2021-10-26

Applicant: Micron Technology, Inc.

Inventor： Jaeil Kim

IPC: G11C7/22 ,  G11C11/4076 ,  G11C11/408 ,  G11C29/02 ,  G11C29/50 ,  G11C11/4093

CPC classification number: G11C11/4076 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4087 ,  G11C29/023 ,  G11C29/50012 ,  G11C11/4093 ,  G11C2207/2254

Abstract: Methods, systems, and devices for timing signal calibration for a memory device are described. In some memory devices, operations for accessing memory cells may be performed with timing that is asynchronous with an input signal. To support asynchronous timing, a timing signal generation component of a memory device may include delay components that support generating a timing signal having aspects that are delayed relative to an input signal. Delay components may have characteristics that are sensitive to fabrication or operational variability, such that timing signals may also be affected by such variability. In accordance with examples as disclosed herein, a memory device may include delay components, associated with access operation timing signal generation, that are configured to be selectively enabled or disabled based on a calibration operation of the memory device, which may improve an ability of the memory device to account for various sources of timing signal variability.

公开(公告)号：US11164620B1

公开(公告)日：2021-11-02

申请号：US16891601

申请日：2020-06-03

Applicant: Micron Technology, Inc.

Inventor： Jaeil Kim

IPC: G11C7/22 ,  G11C11/4076 ,  G11C11/408 ,  G11C29/02 ,  G11C29/50 ,  G11C11/4093

Abstract: Methods, systems, and devices for timing signal calibration for a memory device are described. In some memory devices, operations for accessing memory cells may be performed with timing that is asynchronous with an input signal. To support asynchronous timing, a timing signal generation component of a memory device may include delay components that support generating a timing signal having aspects that are delayed relative to an input signal. Delay components may have characteristics that are sensitive to fabrication or operational variability, such that timing signals may also be affected by such variability. In accordance with examples as disclosed herein, a memory device may include delay components, associated with access operation timing signal generation, that are configured to be selectively enabled or disabled based on a calibration operation of the memory device, which may improve an ability of the memory device to account for various sources of timing signal variability.

公开(公告)号：US20240071471A1

公开(公告)日：2024-02-29

申请号：US17900075

申请日：2022-08-31

Applicant: Micron Technology, Inc.

Inventor： Jaeil Kim

IPC: G11C11/409 ,  G06F11/10 ,  G11C11/408

CPC classification number: G11C11/409 ,  G06F11/1044 ,  G11C11/4085

Abstract: A memory device comprises memory and control circuitry. The control circuitry can receive a command to access the memory. Responsive to receiving the command to access the memory, the control circuitry can provide command data of the command to pipelatch circuitry and error correction code (ECC) circuitry. The memory device further includes pipelatch circuitry to receive command data of the command from the control circuitry and maintain the command data for a period of time of a duration longer than error calculation time of the ECC circuitry.

公开(公告)号：US20240070058A1

公开(公告)日：2024-02-29

申请号：US18234636

申请日：2023-08-16

Applicant: Micron Technology, Inc.

Inventor： Jaeil Kim

IPC: G06F12/02 ,  G11C11/22 ,  G11C11/4096

CPC classification number: G06F12/023 ,  G11C11/2273 ,  G11C11/4096 ,  G11C11/4076

Abstract: A system includes memory having a bank area and a channel area. The system further includes control circuitry to receive a command to access the memory. Responsive to receiving the command to access the memory, the control circuitry can provide a bank strobe signal for accessing memory in the bank area and at least two channel strobe signals for accessing memory in the channel area. The channel strobe signal may process a smaller amount of data than that processed by the bank strobe signal.