公开(公告)号：US20240029767A1

公开(公告)日：2024-01-25

申请号：US17868695

申请日：2022-07-19

Applicant: Micron Technology, Inc.

Inventor： Mark K. Hadrick

IPC: G11C7/10

CPC classification number: G11C7/1093 ,  G11C7/1084 ,  G11C7/1096 ,  G11C7/1087

Abstract: Methods, apparatuses, and systems related to die-to-die communications are described. An apparatus may include a master die and a slave die communicatively coupled to each other through an internal bus. The apparatus can be configured to use an internal command and/or a data clock to coordinate the storage/write operation at the slave die instead of or in addition to a command address clock.

公开(公告)号：US09508409B2

公开(公告)日：2016-11-29

申请号：US14254378

申请日：2014-04-16

Applicant: Micron Technology, Inc.

Inventor： Mark K. Hadrick ,  Jeffrey P. Wright ,  Victor Wong ,  Simon J. Lovett ,  Donald M. Morgan ,  William F. Jones ,  Sujeet Ayyapureddi ,  Dean D. Gans ,  Jongtae Kwak

IPC: G11C7/22 ,  G11C7/10 ,  G11C8/12

CPC classification number: G11C7/22 ,  G11C7/1009 ,  G11C7/1042 ,  G11C8/12 ,  G11C2207/229

Abstract: Apparatuses and methods for implementing masked write commands are disclosed herein. An example apparatus may include a memory bank, a local buffer circuit, and an address control circuit. The local buffer circuit may be associated with the memory bank. The address control circuit may be coupled to the memory bank and configured to receive a command and an address associated with the command. The address control circuit may include a global buffer circuit configured to store the address. The address control circuit may further be configured to delay the command using one of a plurality of command paths based, at least in part, on a write latency and to provide the address stored in the global buffer circuit to the local buffer circuit to be stored therein.

Abstract translation: 本文公开了用于实现屏蔽写入命令的装置和方法。 示例性装置可以包括存储体，局部缓冲电路和地址控制电路。 本地缓冲电路可以与存储体相关联。 地址控制电路可以耦合到存储体并被配置为接收命令和与该命令相关联的地址。 地址控制电路可以包括被配置为存储地址的全局缓冲电路。 地址控制电路还可以被配置为至少部分地基于写等待时间来延迟使用多个命令路径之一的命令，并且将存储在全局缓冲器电路中的地址提供给要存储的本地缓冲器电路 其中。

公开(公告)号：US10388362B1

公开(公告)日：2019-08-20

申请号：US15974120

申请日：2018-05-08

Applicant: Micron Technology, Inc.

Inventor： Mark K. Hadrick

IPC: G11C11/4093 ,  G11C11/4076 ,  G11C11/408 ,  G11C29/42 ,  G11C11/4096

Abstract: Memory devices with half-width data path or data buses clocked by double-pumped strobe signals are disclosed herein. The methods and devices may employ a single delay chain (e.g., a column access strobe (CAS) chain) to perform the double-pumped operations. The delay chain may include multiple delay elements that may generate one or two pulses based on the double-pumped strobe signals. Methods for interfacing, such as read and write methods are also disclosed.

公开(公告)号：US10832759B2

公开(公告)日：2020-11-10

申请号：US16526681

申请日：2019-07-30

Applicant: Micron Technology, Inc.

Inventor： Mark K. Hadrick

IPC: G11C11/4096 ,  G11C11/4093 ,  G11C11/4076 ,  G11C11/408 ,  G11C29/42

Abstract: Memory devices with half-width data path or data buses clocked by double-pumped strobe signals are disclosed herein. The methods and devices may employ a single delay chain (e.g., a column access strobe (CAS) chain) to perform the double-pumped operations. The delay chain may include multiple delay elements that may generate one or two pulses based on the double-pumped strobe signals. Methods for interfacing, such as read and write methods are also disclosed.

公开(公告)号：US20190355410A1

公开(公告)日：2019-11-21

申请号：US16526681

申请日：2019-07-30

Applicant: Micron Technology, Inc.

Inventor： Mark K. Hadrick

IPC: G11C11/4093 ,  G11C11/4096 ,  G11C11/4076 ,  G11C11/408 ,  G11C29/42

Abstract: Memory devices with half-width data path or data buses clocked by double-pumped strobe signals are disclosed herein. The methods and devices may employ a single delay chain (e.g., a column access strobe (CAS) chain) to perform the double-pumped operations. The delay chain may include multiple delay elements that may generate one or two pulses based on the double-pumped strobe signals. Methods for interfacing, such as read and write methods are also disclosed.

公开(公告)号：US20250157528A1

公开(公告)日：2025-05-15

申请号：US18923616

申请日：2024-10-22

Applicant: Micron Technology, Inc.

Inventor： Keun-Soo Song ,  Mark K. Hadrick

IPC: G11C11/4096 ,  G11C11/4093

Abstract: Methods, apparatuses, and systems related to operations for executing mode register read and mode register write all commands. A memory device can execute a register read or a mode register write all command using a unit interval of one or more DQs. One or more command address pins can be designated to store groups of mode registers. The memory device can read or write mode register information associated with the group of mode registers through a pre-defined number of DQs, burst length, and die configuration.

公开(公告)号：US20250157527A1

公开(公告)日：2025-05-15

申请号：US18923597

申请日：2024-10-22

Applicant: Micron Technology, Inc.

Inventor： Keun-Soo Song ,  Mark K. Hadrick

IPC: G11C11/4096 ,  G11C11/4093

Abstract: Methods, apparatuses, and systems related to operations for executing mode register read and mode register write all commands. A memory device can execute a register read or a mode register write all command using a unit interval of one or more DQs. One or more command address pins can be designated to store groups of mode registers. The memory device can read or write mode register information associated with the group of mode registers through a pre-defined number of DQs, burst length, and die configuration.

公开(公告)号：US20150302907A1

公开(公告)日：2015-10-22

申请号：US14254378

申请日：2014-04-16

Applicant: Micron Technology, Inc.

Inventor： Mark K. Hadrick ,  Jeffrey P. Wright ,  Victor Wong ,  Simon J. Lovett ,  Donald M. Morgan ,  William F. Jones ,  Sujeet Ayyapureddi ,  Dean D. Gans ,  Jongtae Kwak

IPC: G11C8/06 ,  G11C7/22

CPC classification number: G11C7/22 ,  G11C7/1009 ,  G11C7/1042 ,  G11C8/12 ,  G11C2207/229

Abstract: Apparatuses and methods for implementing masked write commands are disclosed herein. An example apparatus may include a memory bank, a local buffer circuit, and an address control circuit. The local buffer circuit may be associated with the memory bank. The address control circuit may be coupled to the memory bank and configured to receive a command and an address associated with the command. The address control circuit may include a global buffer circuit configured to store the address. The address control circuit may further be configured to delay the command using one of a plurality of command paths based, at least in part, on a write latency and to provide the address stored in the global buffer circuit to the local buffer circuit to be stored therein.

Abstract translation: 本文公开了用于实现屏蔽写入命令的装置和方法。 示例性装置可以包括存储体，局部缓冲电路和地址控制电路。 本地缓冲电路可以与存储体相关联。 地址控制电路可以耦合到存储体并被配置为接收命令和与命令相关联的地址。 地址控制电路可以包括被配置为存储地址的全局缓冲电路。 地址控制电路还可以被配置为至少部分地基于写等待时间来延迟使用多个命令路径之一的命令，并且将存储在全局缓冲器电路中的地址提供给要存储的本地缓冲器电路 其中。