公开(公告)号：US20190296016A1

公开(公告)日：2019-09-26

申请号：US16436689

申请日：2019-06-10

Applicant: Micron Technology, Inc.

Inventor： Rajesh N. Gupta ,  Farid Nemati ,  Scott T. Robins

IPC: H01L27/102 ,  H01L21/8229 ,  H01L29/73 ,  H01L29/739 ,  H01L29/16 ,  H01L29/732 ,  H01L21/02 ,  H01L29/735

Abstract: Some embodiments include gated bipolar junction transistors. The transistors may include a base region between a collector region and an emitter region; with a B-C junction being at an interface of the base region and the collector region, and with a B-E junction being at an interface of the base region and the emitter region. The transistors may include material having a bandgap of at least 1.2 eV within one or more of the base, emitter and collector regions. The gated transistors may include a gate along the base region and spaced from the base region by dielectric material, with the gate not overlapping either the B-C junction or the B-E junction. Some embodiments include memory arrays containing gated bipolar junction transistors. Some embodiments include methods of forming gated bipolar junction transistors.

公开(公告)号：US20160078917A1

公开(公告)日：2016-03-17

申请号：US14948097

申请日：2015-11-20

Applicant: Micron Technology, Inc.

Inventor： Farid Nemati ,  Scott T. Robins ,  Rajesh N. Gupta

IPC: G11C11/39

CPC classification number: G11C11/39 ,  H01L21/28008 ,  H01L21/30604 ,  H01L21/76224 ,  H01L27/0817 ,  H01L27/1027 ,  H01L29/7455 ,  H01L29/749

Abstract: Some embodiments include thyristors having first and second electrode regions, first and second base regions, and material having a bandgap of at least 1.2 eV in at least one of the regions. The first base region is between the first electrode region and the second base region, and the second base region is between the second electrode region and the first base region. The first base region interfaces with the first electrode region at a first junction, and interfaces with the second base region at a second junction. The second base region interfaces with the second electrode region at a third junction. A gate is along the first base region, and in some embodiments does not overlap either of the first and second junctions. Some embodiments include methods of programming thyristors, and some embodiments include methods of forming thyristors.

Abstract translation: 一些实施例包括具有第一和第二电极区域，第一和第二基极区域以及在至少一个区域中具有至少1.2eV的带隙的材料的晶闸管。 第一基极区域在第一电极区域和第二基极区域之间，第二基极区域在第二电极区域和第一基极区域之间。 第一基区在第一结处与第一电极区相接，并且在第二结处与第二基区交界。 第二基极区域在第三结区与第二电极区域相接合。 栅极沿着第一基极区域，并且在一些实施例中不与第一和第二结点重叠。 一些实施例包括编程晶闸管的方法，并且一些实施例包括形成晶闸管的方法。

公开(公告)号：US10373956B2

公开(公告)日：2019-08-06

申请号：US14613876

申请日：2015-02-04

Applicant: Micron Technology, Inc.

Inventor： Rajesh N. Gupta ,  Farid Nemati ,  Scott T. Robins

IPC: H01L29/74 ,  H01L27/102 ,  H01L29/73 ,  H01L29/735 ,  H01L21/02 ,  H01L21/8229 ,  H01L29/16 ,  H01L29/732 ,  H01L29/739 ,  H01L27/108 ,  H01L29/78

Abstract: Some embodiments include gated bipolar junction transistors. The transistors may include a base region between a collector region and an emitter region; with a B-C junction being at an interface of the base region and the collector region, and with a B-E junction being at an interface of the base region and the emitter region. The transistors may include material having a bandgap of at least 1.2 eV within one or more of the base, emitter and collector regions. The gated transistors may include a gate along the base region and spaced from the base region by dielectric material, with the gate not overlapping either the B-C junction or the B-E junction. Some embodiments include memory arrays containing gated bipolar junction transistors. Some embodiments include methods of forming gated bipolar junction transistors.

公开(公告)号：US09691465B2

公开(公告)日：2017-06-27

申请号：US14948097

申请日：2015-11-20

Applicant: Micron Technology, Inc.

Inventor： Farid Nemati ,  Scott T. Robins ,  Rajesh N. Gupta

IPC: H01L21/28 ,  G11C11/39 ,  H01L27/08 ,  H01L27/102 ,  H01L29/745 ,  H01L21/306 ,  H01L21/762 ,  H01L29/749

CPC classification number: G11C11/39 ,  H01L21/28008 ,  H01L21/30604 ,  H01L21/76224 ,  H01L27/0817 ,  H01L27/1027 ,  H01L29/7455 ,  H01L29/749

Abstract: Some embodiments include thyristors having first and second electrode regions, first and second base regions, and material having a bandgap of at least 1.2 eV in at least one of the regions. The first base region is between the first electrode region and the second base region, and the second base region is between the second electrode region and the first base region. The first base region interfaces with the first electrode region at a first junction, and interfaces with the second base region at a second junction. The second base region interfaces with the second electrode region at a third junction. A gate is along the first base region, and in some embodiments does not overlap either of the first and second junctions. Some embodiments include methods of programming thyristors, and some embodiments include methods of forming thyristors.

公开(公告)号：US09361966B2

公开(公告)日：2016-06-07

申请号：US13957304

申请日：2013-08-01

Applicant: Micron Technology, Inc.

Inventor： Farid Nemati ,  Scott T. Robins ,  Rajesh N. Gupta

IPC: H01L21/332 ,  G11C11/39 ,  H01L27/08 ,  H01L27/102 ,  H01L29/745 ,  H01L21/28

CPC classification number: G11C11/39 ,  H01L21/28008 ,  H01L21/30604 ,  H01L21/76224 ,  H01L27/0817 ,  H01L27/1027 ,  H01L29/7455 ,  H01L29/749

Abstract: Some embodiments include thyristors having first and second electrode regions, first and second base regions, and material having a bandgap of at least 1.2 eV in at least one of the regions. The first base region is between the first electrode region and the second base region, and the second base region is between the second electrode region and the first base region. The first base region interfaces with the first electrode region at a first junction, and interfaces with the second base region at a second junction. The second base region interfaces with the second electrode region at a third junction. A gate is along the first base region, and in some embodiments does not overlap either of the first and second junctions. Some embodiments include methods of programming thyristors, and some embodiments include methods of forming thyristors.

公开(公告)号：US10886273B2

公开(公告)日：2021-01-05

申请号：US16436689

申请日：2019-06-10

Applicant: Micron Technology, Inc.

Inventor： Rajesh N. Gupta ,  Farid Nemati ,  Scott T. Robins

IPC: H01L21/8249 ,  H01L27/102 ,  H01L29/735 ,  H01L29/73 ,  H01L21/02 ,  H01L21/8229 ,  H01L29/16 ,  H01L29/732 ,  H01L29/739 ,  H01L27/108 ,  H01L29/78

Abstract: Some embodiments include gated bipolar junction transistors. The transistors may include a base region between a collector region and an emitter region; with a B-C junction being at an interface of the base region and the collector region, and with a B-E junction being at an interface of the base region and the emitter region. The transistors may include material having a bandgap of at least 1.2 eV within one or more of the base, emitter and collector regions. The gated transistors may include a gate along the base region and spaced from the base region by dielectric material, with the gate not overlapping either the B-C junction or the B-E junction. Some embodiments include memory arrays containing gated bipolar junction transistors. Some embodiments include methods of forming gated bipolar junction transistors.

公开(公告)号：US20150155283A1

公开(公告)日：2015-06-04

申请号：US14613876

申请日：2015-02-04

Applicant: Micron Technology, Inc.

Inventor： Rajesh N. Gupta ,  Farid Nemati ,  Scott T. Robins

IPC: H01L27/102 ,  H01L21/8229 ,  H01L21/02 ,  H01L29/732 ,  H01L29/739 ,  H01L29/16

CPC classification number: H01L27/1026 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/8229 ,  H01L27/1023 ,  H01L27/1024 ,  H01L27/10802 ,  H01L29/1608 ,  H01L29/73 ,  H01L29/732 ,  H01L29/735 ,  H01L29/7391 ,  H01L29/7841 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments include gated bipolar junction transistors. The transistors may include a base region between a collector region and an emitter region; with a B-C junction being at an interface of the base region and the collector region, and with a B-E junction being at an interface of the base region and the emitter region. The transistors may include material having a bandgap of at least 1.2 eV within one or more of the base, emitter and collector regions. The gated transistors may include a gate along the base region and spaced from the base region by dielectric material, with the gate not overlapping either the B-C junction or the B-E junction. Some embodiments include memory arrays containing gated bipolar junction transistors. Some embodiments include methods of forming gated bipolar junction transistors.

Abstract translation: 一些实施例包括门极双极结型晶体管。 晶体管可以包括在集电极区域和发射极区域之间的基极区域; 其中B-C结位于基极区和集电极区的界面处，并且B-E结位于基极区和发射极区的界面处。 晶体管可以包括在一个或多个基极，发射极和集电极区内具有至少1.2eV的带隙的材料。 栅极晶体管可以包括沿着基极区域的栅极并且通过电介质材料与基极区域间隔开，栅极不与B-C结或B-E结重叠。 一些实施例包括包含门极双极结型晶体管的存储器阵列。 一些实施例包括形成门控双极结型晶体管的方法。

公开(公告)号：US20130314986A1

公开(公告)日：2013-11-28

申请号：US13957304

申请日：2013-08-01

Applicant: Micron Technology, Inc.

Inventor： Farid Nemati ,  Scott T. Robins ,  Rajesh N. Gupta

IPC: G11C11/39 ,  H01L21/28

CPC classification number: G11C11/39 ,  H01L21/28008 ,  H01L21/30604 ,  H01L21/76224 ,  H01L27/0817 ,  H01L27/1027 ,  H01L29/7455 ,  H01L29/749

Abstract: Some embodiments include thyristors having first and second electrode regions, first and second base regions, and material having a bandgap of at least 1.2 eV in at least one of the regions. The first base region is between the first electrode region and the second base region, and the second base region is between the second electrode region and the first base region. The first base region interfaces with the first electrode region at a first junction, and interfaces with the second base region at a second junction. The second base region interfaces with the second electrode region at a third junction. A gate is along the first base region, and in some embodiments does not overlap either of the first and second junctions. Some embodiments include methods of programming thyristors, and some embodiments include methods of forming thyristors.

Abstract translation: 一些实施例包括具有第一和第二电极区域，第一和第二基极区域以及在至少一个区域中具有至少1.2eV的带隙的材料的晶闸管。 第一基极区域在第一电极区域和第二基极区域之间，第二基极区域在第二电极区域和第一基极区域之间。 第一基区在第一结处与第一电极区相接，并且在第二结处与第二基区交界。 第二基极区域在第三结区与第二电极区域相接合。 栅极沿着第一基极区域，并且在一些实施例中不与第一和第二结点重叠。 一些实施例包括编程晶闸管的方法，一些实施例包括形成晶闸管的方法。