公开(公告)号：US20240256448A1

公开(公告)日：2024-08-01

申请号：US18414640

申请日：2024-01-17

Applicant: Micron Technology, Inc.

Inventor： Peter L. Brown ,  Glen E. Hush ,  Troy A. Manning ,  Timothy P. Finkbeiner ,  Troy D. Larsen

IPC: G06F12/0802

CPC classification number: G06F12/0802 ,  G06F2212/1032 ,  G06F2212/221

Abstract: Methods, systems, and devices related to sense amplifiers of a memory device serving as a Static Random Access Memory (SRAM) cache. For example, a memory array can be coupled to sense amplifiers. In a first mode, the sense amplifiers can be electrically disconnect from digit lines of the memory array. In the first mode, data and metadata of a cache line can be stored in the sense amplifiers when electrically disconnected from the number of digit lines. In the first mode, a portion of the data can be communicated, based on the metadata, from the sense amplifiers to the processing device. In a second mode, the sense amplifiers can connect to the memory array and sense data from the memory array.

公开(公告)号：US11837315B2

公开(公告)日：2023-12-05

申请号：US17855212

申请日：2022-06-30

Applicant: Micron Technology, Inc.

Inventor： Timothy P. Finkbeiner ,  Troy A. Manning ,  Troy D. Larsen ,  Glen E. Hush

IPC: G11C7/06 ,  G11C7/10

CPC classification number: G11C7/065 ,  G11C7/1039 ,  G11C7/1075 ,  G11C7/1096

Abstract: Methods and devices related to transferring data between DRAM and SRAM. One method includes activating a first portion of a dynamic random access memory (DRAM), reading data from the first portion of the DRAM, latching the data from the first portion of the DRAM in one or more sense amplifiers, and writing the data from the one or more sense amplifiers to a first portion of a static random access memory (SRAM).

公开(公告)号：US20230070383A1

公开(公告)日：2023-03-09

申请号：US17985304

申请日：2022-11-11

Applicant: Micron Technology, Inc.

Inventor： Perry V. Lea ,  Troy A. Manning

IPC: G11C7/10 ,  G06F13/12 ,  G11C8/12 ,  G11C11/4096 ,  H03K19/173 ,  G11C11/408

Abstract: The present disclosure includes apparatuses and methods for bank to bank data transfer. An example apparatus includes a plurality of banks of memory cells, an internal bus configured to transfer data between the plurality of banks and an external bus interface, and a bank-to-bank transfer bus configured to transfer data between the plurality of banks.

公开(公告)号：US11495274B2

公开(公告)日：2022-11-08

申请号：US17135802

申请日：2020-12-28

Applicant: Micron Technology, Inc.

Inventor： Troy A. Manning

IPC: G11C7/22 ,  G11C7/06 ,  G11C11/4074 ,  G11C11/4091 ,  G11C7/10 ,  G06F12/00 ,  G06F3/06 ,  G06F7/523 ,  H03K19/1776 ,  H03K19/00

Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry comprising a primary latch coupled to a sense line of the array. The sensing circuitry can be configured to perform a first operation phase of a logical operation by sensing a memory cell coupled to the sense line, perform a number of intermediate operation phases of the logical operation by sensing a respective number of different memory cells coupled to the sense line, and accumulate a result of the first operation phase and the number of intermediate operation phases in a secondary latch coupled to the primary latch without performing a sense line address access.

公开(公告)号：US20220199128A1

公开(公告)日：2022-06-23

申请号：US17693994

申请日：2022-03-14

Applicant: Micron Technology, Inc.

Inventor： Troy A. Manning

IPC: G11C7/06 ,  G06F12/00 ,  G11C7/10 ,  G11C11/4093 ,  G11C11/4096 ,  G11C15/00 ,  G11C11/4091

Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry is configured to perform a logical operation using a data value stored in a first memory cell coupled to a sense line as a first input and a data value stored in a second memory cell coupled to the sense line as a second input. The sensing circuitry is configured to perform the logical operation without transferring data via a sense line address access.

公开(公告)号：US20200272538A1

公开(公告)日：2020-08-27

申请号：US16871641

申请日：2020-05-11

Applicant: Micron Technology, Inc.

Inventor： Troy A. Manning ,  Troy D. Larsen ,  Martin L. Culley

IPC: G06F11/10 ,  G06F3/06 ,  G11C29/52

Abstract: The present disclosure includes apparatuses and methods for physical page, logical page, and codeword correspondence. A number of methods include error coding a number of logical pages of data as a number of codewords and writing the number of codewords to a number of physical pages of memory. The number of logical pages of data can be different than the number of physical pages of memory.

公开(公告)号：US10726919B2

公开(公告)日：2020-07-28

申请号：US15941896

申请日：2018-03-30

Applicant: Micron Technology, Inc.

Inventor： Troy A. Manning

IPC: G11C15/04 ,  G11C7/10 ,  G11C11/4091

Abstract: Apparatuses and methods related to comparing data patterns in memory. An example method can include comparing a number of data patterns stored in a memory array to a target data pattern. The method can include determining whether a data pattern of the number of data patterns matches the target data pattern.

公开(公告)号：US20200027487A1

公开(公告)日：2020-01-23

申请号：US16587651

申请日：2019-09-30

Applicant: Micron Technology, Inc.

Inventor： Troy A. Manning

IPC: G11C7/06 ,  G06F12/00 ,  G11C7/10 ,  G11C15/00 ,  G11C11/4096 ,  G11C11/4091 ,  G11C11/4093

Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry is configured to perform a logical operation using a data value stored in a first memory cell coupled to a sense line as a first input and a data value stored in a second memory cell coupled to the sense line as a second input. The sensing circuitry is configured to perform the logical operation without transferring data via a sense line address access.

公开(公告)号：US20190237129A1

公开(公告)日：2019-08-01

申请号：US15884179

申请日：2018-01-30

Applicant: Micron Technology, Inc.

Inventor： Troy A. Manning ,  Glen E. Hush

IPC: G11C11/4091 ,  H03K19/0948 ,  H03K19/20 ,  G11C11/4097

CPC classification number: G11C11/4091 ,  G11C11/4097 ,  H03K19/0948 ,  H03K19/20

Abstract: The present disclosure includes apparatuses and methods related to logical operations using memory cells. An example apparatus comprises a first memory cell controlled to invert a data value stored therein and a second memory cell controlled to invert a data value stored therein. The apparatus may further include a controller coupled to the first memory cell and the second memory cell. The controller may be configured to cause performance of a logical operation between the data value stored in the first memory cell and the data value stored in the second memory cell.

公开(公告)号：US20190198070A1

公开(公告)日：2019-06-27

申请号：US16253750

申请日：2019-01-22

Applicant: Micron Technology, Inc.

Inventor： Troy A. Manning

IPC: G11C7/22 ,  G11C7/06 ,  G06F3/06 ,  H03K19/177 ,  H03K19/00 ,  G11C7/10 ,  G06F12/00 ,  G11C11/4091 ,  G06F7/523 ,  G11C11/4074

CPC classification number: G11C7/22 ,  G06F3/0611 ,  G06F3/0625 ,  G06F3/065 ,  G06F3/068 ,  G06F7/523 ,  G06F12/00 ,  G11C7/06 ,  G11C7/065 ,  G11C7/1087 ,  G11C11/4074 ,  G11C11/4091 ,  H03K19/0013 ,  H03K19/1776

Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry comprising a primary latch coupled to a sense line of the array. The sensing circuitry can be configured to perform a first operation phase of a logical operation by sensing a memory cell coupled to the sense line, perform a number of intermediate operation phases of the logical operation by sensing a respective number of different memory cells coupled to the sense line, and accumulate a result of the first operation phase and the number of intermediate operation phases in a secondary latch coupled to the primary latch without performing a sense line address access.