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    Cross-point memory compensation
    1.
    发明授权
    Cross-point memory compensation 有权

    公开(公告)号：US11587615B2

    公开(公告)日：2023-02-21

    申请号：US17316271

    申请日：2021-05-10

    Applicant: Micron Technology, Inc.

    Inventor： Zengtao T. Liu ,  Kirk D. Prall

    IPC: G11C13/00 ,  G11C8/08

    Abstract: The apparatuses and methods described herein may operate to measure a voltage difference between a selected access line and a selected sense line associated with a selected cell of a plurality of memory cells of a memory array. The voltage difference may be compared with a reference voltage specified for a memory operation. A selection voltage(s) applied to the selected cell for the memory operation may be adjusted responsive to the comparison, such as to dynamically compensate for parasitic voltage drop.

    Arrays of Memory Cells and Methods of Forming an Array of Vertically Stacked Tiers of Memory Cells
    2.
    发明申请
    Arrays of Memory Cells and Methods of Forming an Array of Vertically Stacked Tiers of Memory Cells 有权

    公开(公告)号：US20220157888A1

    公开(公告)日：2022-05-19

    申请号：US17589683

    申请日：2022-01-31

    Applicant: Micron Technology, Inc.

    Inventor： Zengtao T. Liu

    IPC: H01L27/24 ,  H01L45/00

    Abstract: An array of vertically stacked tiers of memory cells includes a plurality of horizontally oriented access lines within individual tiers of memory cells and a plurality of horizontally oriented global sense lines elevationally outward of the tiers. A plurality of select transistors is elevationally inward of the tiers. A plurality of pairs of local first and second vertical lines extends through the tiers. The local first vertical line within individual of the pairs is in conductive connection with one of the global sense lines and in conductive connection with one of the two source/drain regions of one of the select transistors. The local second vertical line within individual of the pairs is in conductive connection with another of the two source/drain regions of the one select transistor. Individual of the memory cells include a crossing one of the local second vertical lines and one of the horizontal access lines and programmable material there-between. Other aspects and implementations, including methods, are disclosed.

    Arrays of memory cells and methods of forming an array of vertically stacked tiers of memory cells
    3.
    发明授权
    Arrays of memory cells and methods of forming an array of vertically stacked tiers of memory cells 有权

    公开(公告)号：US11276733B2

    公开(公告)日：2022-03-15

    申请号：US16283645

    申请日：2019-02-22

    Applicant: Micron Technology, Inc.

    Inventor： Zengtao T. Liu

    IPC: H01L27/24 ,  H01L45/00

    Abstract: An array of vertically stacked tiers of memory cells includes a plurality of horizontally oriented access lines within individual tiers of memory cells and a plurality of horizontally oriented global sense lines elevationally outward of the tiers. A plurality of select transistors is elevationally inward of the tiers. A plurality of pairs of local first and second vertical lines extends through the tiers. The local first vertical line within individual of the pairs is in conductive connection with one of the global sense lines and in conductive connection with one of the two source/drain regions of one of the select transistors. The local second vertical line within individual of the pairs is in conductive connection with another of the two source/drain regions of the one select transistor. Individual of the memory cells include a crossing one of the local second vertical lines and one of the horizontal access lines and programmable material there-between. Other aspects and implementations, including methods, are disclosed.

    Memory Arrays
    4.
    发明申请
    Memory Arrays 审中-公开

    公开(公告)号：US20200249307A1

    公开(公告)日：2020-08-06

    申请号：US16850293

    申请日：2020-04-16

    Applicant: Micron Technology, Inc.

    Inventor： Zengtao T. Liu

    IPC: G01R33/58 ,  G11C13/00 ,  G11C7/10 ,  H01L27/24 ,  G11C5/06 ,  H01L45/00 ,  G11C5/02 ,  G01R33/12 ,  G11C8/14

    Abstract: Some embodiments include memory arrays. The memory arrays can have global bitlines extending along a first horizontal direction, vertical local bitlines extending perpendicularly from the global bitlines, and wordlines extending along a second horizontal direction which is perpendicular to the first horizontal direction. The global bitlines may be subdivided into a first series at a first elevational level, and a second series at a second elevational level which is different from the first elevational level. The global bitlines of the first series can alternate with the global bitlines of the second series. There can be memory cell material directly between the wordlines and the vertical local bitlines. The memory cell material may form a plurality of memory cells uniquely addressed by wordline/global bitline combinations. Some embodiments include cross-point memory cell units that have areas of about 2F2.

    Semiconductor Constructions and Methods of Forming Semiconductor Constructions
    8.
    发明申请
    Semiconductor Constructions and Methods of Forming Semiconductor Constructions 有权
    半导体结构和形成半导体结构的方法

    公开(公告)号：US20140145344A1

    公开(公告)日：2014-05-29

    申请号：US14168898

    申请日：2014-01-30

    Applicant: Micron Technology, Inc.

    Inventor： Zengtao T. Liu

    IPC: H01L23/48

    CPC classification number: H01L23/481 ,  H01L21/76829 ,  H01L21/76897 ,  H01L23/482 ,  H01L27/1052 ,  H01L27/10876 ,  H01L27/10894 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Some embodiments include methods in which first insulative material is formed across a memory region and a peripheral region of a substrate. An etch stop structure is formed to have a higher portion over the memory region than over the peripheral region. A second insulative material is formed to protect the lower portion of the etch stop structure, and the higher portion is removed. Subsequently, at least some of the first and second insulative materials are removed. Some embodiments include semiconductor constructions having a first region with first features, and a second region with second features. The first features are closer spaced than the second features. A first insulative material is over the second region and an insulative structure is over the first insulative material. The structure has a stem joined to a bench. The bench has an upper surface, and the stem extends to above the upper surface.

    Abstract translation: 一些实施方案包括其中在衬底的存储区和外围区域形成第一绝缘材料的方法。 蚀刻停止结构形成为在存储区域上比在周边区域上具有更高的部分。 形成第二绝缘材料以保护蚀刻停止结构的下部，并且去除较高部分。 随后，去除第一和第二绝缘材料中的至少一些。 一些实施例包括具有具有第一特征的第一区域和具有第二特征的第二区域的半导体结构。 第一特征与第二特征相距更近。 第一绝缘材料在第二区域之上，绝缘结构超过第一绝缘材料。 该结构具有连接到工作台的杆。 工作台具有上表面，并且杆延伸到上表面上方。

    Memory Arrays
    9.
    发明申请
    Memory Arrays 有权
    记忆阵列

    公开(公告)号：US20130294132A1

    公开(公告)日：2013-11-07

    申请号：US13937994

    申请日：2013-07-09

    Applicant: Micron Technology, Inc.

    Inventor： Zengtao T. Liu

    IPC: G11C5/02

    CPC classification number: G01R33/58 ,  G01R33/1284 ,  G01R33/24 ,  G11C5/025 ,  G11C5/063 ,  G11C7/1087 ,  G11C7/1093 ,  G11C8/14 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/003 ,  G11C2213/18 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/77 ,  H01L27/2409 ,  H01L27/2427 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/14 ,  H01L45/144

    Abstract: Some embodiments include memory arrays. The memory arrays can have global bitlines extending along a first horizontal direction, vertical local bitlines extending perpendicularly from the global bitlines, and wordlines extending along a second horizontal direction which is perpendicular to the first horizontal direction. The global bitlines may be subdivided into a first series at a first elevational level, and a second series at a second elevational level which is different from the first elevational level. The global bitlines of the first series can alternate with the global bitlines of the second series. There can be memory cell material directly between the wordlines and the vertical local bitlines. The memory cell material may form a plurality of memory cells uniquely addressed by wordline/global bitline combinations. Some embodiments include cross-point memory cell units that have areas of about 2F2.

    Abstract translation: 一些实施例包括存储器阵列。 存储器阵列可以具有沿着第一水平方向延伸的全局位线，垂直于全局位线垂直延伸的垂直局部位线以及沿垂直于第一水平方向的第二水平方向延伸的字线。 全局位线可以在第一高度级细分为第一系列，而在第二高度级可以被分为与第一高度不同的第二系列。 第一个系列的全局位线可以与第二个系列的全局位线交替。 直接在字线和垂直的局部位线之间可以存储单元格材料。 存储单元材料可以形成由字线/全局位线组合唯一地寻址的多个存储单元。 一些实施例包括具有约2F2的面积的交叉点存储单元单元。

    Cross-point memory compensation
    10.
    发明授权
    Cross-point memory compensation 有权

    公开(公告)号：US11004510B2

    公开(公告)日：2021-05-11

    申请号：US16895905

    申请日：2020-06-08

    Applicant: Micron Technology, Inc.

    Inventor： Zengtao T. Liu ,  Kirk D. Prall

    IPC: G11C13/00 ,  G11C8/08

    Abstract: The apparatuses and methods described herein may operate to measure a voltage difference between a selected access line and a selected sense line associated with a selected cell of a plurality of memory cells of a memory array. The voltage difference may be compared with a reference voltage specified for a memory operation. A selection voltage(s) applied to the selected cell for the memory operation may be adjusted responsive to the comparison, such as to dynamically compensate for parasitic voltage drop.

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