公开(公告)号：US20200027748A1

公开(公告)日：2020-01-23

申请号：US16586584

申请日：2019-09-27

申请人： Mitsubishi Electric Corporation

发明人： Katsumi NAKAMURA

IPC分类号： H01L21/322 ,  H01L29/739 ,  H01L29/66 ,  H01L21/324 ,  H01L29/06 ,  H01L29/861 ,  H01L29/40 ,  H01L29/32

摘要： A semiconductor device of the present invention includes a substrate having a drift layer, metal wiring formed on an upper surface of the substrate, and an electrode formed on a back surface of the substrate, wherein the lifetime of carriers in the drift layer satisfies the following expression 1:[Expression 1] τ≥1.5×10−5exp(5.4×103tN−)  expression 1 τ: the lifetime of carriers in the drift layer tN−: the layer thickness of the drift layer.

公开(公告)号：US20190123145A1

公开(公告)日：2019-04-25

申请号：US16216815

申请日：2018-12-11

申请人： Mitsubishi Electric Corporation

发明人： Katsumi NAKAMURA

IPC分类号： H01L29/10 ,  H01L21/265 ,  H01L29/66 ,  H01L27/06 ,  H01L29/861 ,  H01L29/36 ,  H01L21/322 ,  H01L21/225 ,  H01L29/868 ,  H01L21/266 ,  H01L21/324 ,  H01L29/739 ,  H01L29/06

CPC分类号： H01L29/1095 ,  H01L21/2253 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/3221 ,  H01L21/324 ,  H01L27/0664 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/36 ,  H01L29/402 ,  H01L29/407 ,  H01L29/66121 ,  H01L29/66348 ,  H01L29/739 ,  H01L29/7397 ,  H01L29/8611 ,  H01L29/868

摘要： The present invention relates to a vertical semiconductor device such as an IGBT or a diode which includes an N buffer layer formed in the undersurface of and adjacent to an N− drift layer. A concentration slope δ, which is derived from displacements in a depth TB (μm) and an impurity concentration CB (cm−3), from the upper surface to the lower surface in a main portion of the N buffer layer satisfies a concentration slope condition defined by {0.03≤δ≤0.7}.

公开(公告)号：US20180248003A1

公开(公告)日：2018-08-30

申请号：US15755098

申请日：2015-12-28

申请人： Mitsubishi Electric Corporation

发明人： Katsumi NAKAMURA ,  Tatsuo HARADA ,  Noritsugu NOMURA

IPC分类号： H01L29/08 ,  H01L29/739 ,  H01L29/861 ,  H01L29/868 ,  H01L21/225 ,  H01L21/04 ,  H01L29/06

CPC分类号： H01L29/083 ,  H01L21/041 ,  H01L21/0455 ,  H01L21/2253 ,  H01L21/2258 ,  H01L21/263 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0688 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/1602 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/36 ,  H01L29/402 ,  H01L29/407 ,  H01L29/66128 ,  H01L29/66348 ,  H01L29/7397 ,  H01L29/78 ,  H01L29/861 ,  H01L29/8611 ,  H01L29/868

摘要： An active cell region, an edge termination region surrounding the active cell region and an intermediate region located at an intermediate position between these regions are provided, the active cell region has a trench gate type MOS structure on a top side, and a vertical structure on a bottom side includes a p-collector layer, an n-buffer layer on the p-collector layer, and an n-drift layer on the n-buffer layer, the n-buffer layer has a first buffer portion provided on the p-collector layer side, and a second buffer portion provided on the n-drift layer side, the peak impurity concentration of the first buffer portion is higher than the peak impurity concentration of the second buffer portion, and the impurity concentration gradient on the n-drift layer side of the second buffer portion is gentler than the impurity concentration gradient on the n-drift layer side of the first buffer portion.

公开(公告)号：US20180019131A1

公开(公告)日：2018-01-18

申请号：US15545732

申请日：2015-03-13

申请人： Mitsubishi Electric Corporation

发明人： Kenji SUZUKI ,  Atsushi NARAZAKI ,  Ryu KAMIBABA ,  Yusuke FUKADA ,  Katsumi NAKAMURA

IPC分类号： H01L21/265 ,  H01L21/268 ,  H01L29/66 ,  H01L29/739 ,  H01L21/283 ,  H01L29/36 ,  H01L29/167 ,  H01L29/10 ,  H01L29/08 ,  H01L21/324 ,  H01L29/861 ,  H01L29/417 ,  H01L29/45 ,  H01L29/06

CPC分类号： H01L21/26513 ,  H01L21/26506 ,  H01L21/268 ,  H01L21/283 ,  H01L21/324 ,  H01L29/0696 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/1602 ,  H01L29/167 ,  H01L29/2003 ,  H01L29/36 ,  H01L29/41708 ,  H01L29/456 ,  H01L29/66136 ,  H01L29/66348 ,  H01L29/739 ,  H01L29/7397 ,  H01L29/78 ,  H01L29/861

摘要： A p-type base layer (2) is formed on a surface of an n-type silicon substrate (1). First and second n+-type buffer layers (8,9) 9 are formed on a back surface of the n-type silicon substrate (1). The first n+-type buffer layer (8) is formed by a plurality of implantations of protons at different accelerating voltages and has a plurality of peak concentrations with different depths from the back surface of the n-type silicon substrate (1). The second n+-type buffer layer (9) is formed by an implantation of a phosphorus. A position of a peak concentration of the phosphorus is shallower from the back surface of the n-type silicon substrate (1) than positions of peak concentrations of the protons. The peak concentration of the phosphorus is higher than the peak concentrations of the protons. A concentration of the protons is higher than a concentration of the phosphorus at the positions of the peak concentrations of the protons.

公开(公告)号：US20160204237A1

公开(公告)日：2016-07-14

申请号：US14991473

申请日：2016-01-08

申请人： Mitsubishi Electric Corporation

发明人： Ze CHEN ,  Katsumi NAKAMURA

IPC分类号： H01L29/739 ,  H01L29/40 ,  H01L29/10 ,  H01L29/06

CPC分类号： H01L29/0634 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/4236 ,  H01L29/7397

摘要： A semiconductor device includes a semiconductor substrate in which an active region and an edge termination region are defined, a semiconductor element formed in the active region, and first to fourth P layers formed in a region spanning from an edge portion of the active region to the edge termination region in the surface of the semiconductor substrate. The first to fourth P layers respectively have surface concentrations P(1) to P(4) that decrease in this order, bottom-end distances D(1) to D(4) that increase in this order, and distances B(1) to B(4) to the edge of the semiconductor substrate that increase in this order. The surface concentration P(4) is 10 to 1000 times the impurity concentration of the semiconductor substrate, and the bottom-end distance D(4) is in the range of 15 to 30 μm.

公开(公告)号：US20240178306A1

公开(公告)日：2024-05-30

申请号：US18432923

申请日：2024-02-05

申请人： Mitsubishi Electric Corporation

发明人： Katsumi NAKAMURA

IPC分类号： H01L29/739 ,  H01L29/06 ,  H01L29/66 ,  H01L29/868

CPC分类号： H01L29/7397 ,  H01L29/0696 ,  H01L29/66333 ,  H01L29/868

摘要： A semiconductor device includes: an N− drift layer of a first conductivity type formed in the semiconductor substrate; a P base layer formed on the N− drift layer; and an N buffer layer of the first conductivity type formed under the N− drift layer and higher in peak impurity concentration than the N− drift layer. The N buffer layer includes: a first buffer layer in which a trap level derived from lattice defect is not detected by a photoluminescence method; and a second buffer layer provided between the first buffer layer and the N− drift layer and in which two types of trap levels derived from lattice defect are detected by the photoluminescence method.

公开(公告)号：US20220140118A1

公开(公告)日：2022-05-05

申请号：US17405451

申请日：2021-08-18

申请人： Mitsubishi Electric Corporation

发明人： Katsumi NAKAMURA

IPC分类号： H01L29/739 ,  H01L29/868 ,  H01L29/06 ,  H01L29/66

摘要： A semiconductor device includes: an N− drift layer of a first conductivity type formed in the semiconductor substrate; a P base layer formed on the N− drift layer; and an N buffer layer of the first conductivity type formed under the N− drift layer and higher in peak impurity concentration than the N− drift layer. The N buffer layer includes: a first buffer layer in which a trap level derived from lattice defect is not detected by a photoluminescence method; and a second buffer layer provided between the first buffer layer and the N− drift layer and in which two types of trap levels derived from lattice defect are detected by the photoluminescence method.

公开(公告)号：US20180006160A1

公开(公告)日：2018-01-04

申请号：US15704413

申请日：2017-09-14

申请人： MITSUBISHI ELECTRIC CORPORATION

发明人： Katsumi NAKAMURA

IPC分类号： H01L29/861 ,  H01L29/36 ,  H01L29/739 ,  H01L29/08

摘要： The first layer is located on the first electrode and has the first conductivity type. The second layer is located on the first layer and has the second conductivity type. The third layer is located on the second layer. The second electrode is located on the third layer. The fourth layer is located between the second layer and the third layer, and has the second conductivity type. The third layer includes the first portion and the second portion. The first portion has the second conductivity type and has a peak value of an impurity concentration higher than the peak value of the impurity concentration in the second layer. The second portion has the first conductivity type. The area of the second portion accounts for not less than 20% and not more than 95% of the total area of the first portion and the second portion.

公开(公告)号：US20220285537A1

公开(公告)日：2022-09-08

申请号：US17457320

申请日：2021-12-02

申请人： Mitsubishi Electric Corporation

发明人： Katsumi NAKAMURA

IPC分类号： H01L29/739 ,  H01L29/66

摘要： A semiconductor device includes a semiconductor substrate, a drift layer of a first conductivity type, a buffer layer of the first conductivity type, a first semiconductor layer, and a second semiconductor layer. The first semiconductor layer and the second semiconductor layer are provided on the side of the second main surface of the semiconductor substrate with respect to the buffer layer. The first semiconductor layer and the second semiconductor layer are arranged in this order in a direction from the second main surface toward the first main surface of the semiconductor substrate. The first semiconductor layer and the second semiconductor layer have conductivity types identical to each other. The second semiconductor layer has a larger number of atoms of impurities per unit volume than the first semiconductor layer.

公开(公告)号：US20220059681A1

公开(公告)日：2022-02-24

申请号：US17336012

申请日：2021-06-01

申请人： Mitsubishi Electric Corporation

发明人： Kenji SUZUKI ,  Koichi NISHI ,  Katsumi NAKAMURA ,  Ze CHEN ,  Koji TANAKA

IPC分类号： H01L29/739 ,  H01L29/06 ,  H01L29/66

摘要： A semiconductor device includes an N-type drift layer provided between a first main surface and a second main surface of the semiconductor substrate and an N-type buffer layer provided between the N-type drift layer and the first main surface and having a higher impurity peak concentration than the N-type drift layer. The N-type buffer layer has a structure that a first buffer layer, a second buffer layer, a third buffer layer, and a fourth buffer layer are disposed in this order from a side of the first main surface. When a distance from an impurity peak position of the first buffer layer to an impurity peak position of the second buffer layer is L12 and a distance from an impurity peak position of the second buffer layer to an impurity peak position of the third buffer layer is L23, a relationship of L23/L12≥3.5 is satisfied.