公开(公告)号：US20220190124A1

公开(公告)日：2022-06-16

申请号：US17549566

申请日：2021-12-13

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Shaojun MA ,  Shigeki KOYA ,  Masayuki AOIKE ,  Shinnosuke TAKAHASHI ,  Yasunari UMEMOTO ,  Masatoshi HASE

IPC: H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/737 ,  H03F3/217 ,  H01L29/43

Abstract: A power amplifier that includes a substrate, and an emitter layer, a base layer, and a collector layer laminated in this order on a major surface of the substrate includes an electrical insulator provided adjacent to the emitter layer, an emitter electrode provided between the substrate and both the emitter layer and the electrical insulator, a base electrode electrically connected to the base layer, and a collector electrode electrically connected to the collector layer. The emitter electrode, the electrical insulator, and the base layer are provided between the substrate and the base electrode in a direction perpendicular to the major surface of the substrate.

公开(公告)号：US20220157808A1

公开(公告)日：2022-05-19

申请号：US17504269

申请日：2021-10-18

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Shinnosuke TAKAHASHI ,  Masayuki AOIKE ,  Takayuki TSUTSUI ,  Shigeki KOYA

IPC: H01L27/06 ,  H01L25/18 ,  H01L25/065 ,  H01L25/00 ,  H01L27/02

Abstract: A semiconductor having transistors arranged side by side in one direction over a surface of a substrate and are connected in parallel. At least one passive element is disposed on at least one of regions between two adjacent ones of the transistors. The transistors each include a collector layer over the substrate, a base layer on the collector layer, and an emitter layer on the base layer. Collector electrodes are arranged in such a manner that each of the collector electrodes is located between the substrate and the collector layer of the corresponding one of the transistors and is electrically connected to the collector layer.

公开(公告)号：US20250070732A1

公开(公告)日：2025-02-27

申请号：US18944599

申请日：2024-11-12

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Masao KONDO ,  Shinnosuke TAKAHASHI ,  Shaojun MA

IPC: H03F3/24 ,  H03F1/30

Abstract: A power amplifying circuit includes an output transistor that amplifies a radio frequency signal and outputs an amplified signal, a bias circuit that supplies a bias current or voltage to the output transistor, and a bias control part connected to the bias circuit and includes a control circuit that increases the bias current or voltage when an ambient temperature is equal to or less than a predetermined value. In consecutive time periods of a first, a second, and a third time period, when output of the output transistor in the third time period is greater than output of the output transistor in the first and the second time period, the bias control part increases the bias current or voltage in the second time period as to become higher than the bias current or voltage of a case where the ambient temperature is higher than the predetermined threshold value.

公开(公告)号：US20240096824A1

公开(公告)日：2024-03-21

申请号：US18523320

申请日：2023-11-29

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Masao KONDO ,  Satoshi GOTO ,  Takayuki TSUTSUI ,  Shinnosuke TAKAHASHI

IPC: H01L23/66 ,  H01L25/065 ,  H03F1/56 ,  H03F3/195 ,  H03F3/24

CPC classification number: H01L23/66 ,  H01L25/0657 ,  H03F1/565 ,  H03F3/195 ,  H03F3/245 ,  H01L2223/6611 ,  H01L2223/6655 ,  H01L2225/06503

Abstract: A stacked semiconductor device capable of increasing heat dissipation comprises a first member and a second member. The first member includes a semiconductor substrate and a first electronic circuit. The first electronic circuit includes a semiconductor element provided on one surface of the semiconductor substrate. A second member is attached to a first surface, which is one surface of the first member. The second member includes a second electronic circuit including another semiconductor element. The second member is provided with a first opening that penetrates the second member in a thickness direction. A first conductor projection is coupled to the first electronic circuit. The first conductor projection protrudes from the first surface of the first member through the first opening of the second member to the outside of the first opening.

公开(公告)号：US20220122901A1

公开(公告)日：2022-04-21

申请号：US17504316

申请日：2021-10-18

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Shinnosuke TAKAHASHI ,  Masayuki AOIKE ,  Masatoshi HASE ,  Fumio HARIMA

IPC: H01L23/373 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00

Abstract: A bond layer including at least one metal region in a plan view is disposed on a surface layer portion of a substrate formed from a semiconductor. A semiconductor element is disposed on the bond layer and includes a first transistor disposed on a first metal region that is a metal region as the at least one metal region of the bond layer and including a collector layer electrically coupled to the first metal region, a base layer disposed on the collector layer, and an emitter layer disposed on the base layer. A first emitter electrode is disposed on the emitter layer of the first transistor. A first conductor protrusion is disposed on the first emitter electrode. The thermal conductivity of the semiconductor material of the surface layer portion is higher than that of each of the collector layer, the base layer, and the emitter layer of the first transistor.

公开(公告)号：US20180308926A1

公开(公告)日：2018-10-25

申请号：US15960845

申请日：2018-04-24

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Shinnosuke TAKAHASHI ,  Masayuki AOIKE

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/778 ,  H01L29/423 ,  H01L29/40

CPC classification number: H01L29/0619 ,  H01L21/76 ,  H01L21/76224 ,  H01L29/0626 ,  H01L29/1075 ,  H01L29/1083 ,  H01L29/205 ,  H01L29/405 ,  H01L29/42312 ,  H01L29/42316 ,  H01L29/475 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7781 ,  H01L29/7782 ,  H01L29/7783 ,  H01L29/7786

Abstract: A semiconductor layer arranged on a semiconductor substrate includes an active region and an element isolation region that surrounds the first active region when viewed in plan. A field effect transistor is formed in the active region. A plurality of guard ring electrodes separated from each other affect a potential of the active region through the element isolation region. An interlayer insulating film is formed over the semiconductor layer, the field effect transistor, and the guard ring electrodes. At least one guard ring connection wiring formed on the interlayer insulating film electrically interconnects the plurality of guard ring electrodes.

公开(公告)号：US20250105798A1

公开(公告)日：2025-03-27

申请号：US18975469

申请日：2024-12-10

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Satoshi GOTO ,  Masao KONDO ,  Kenji SASAKI ,  Shinnosuke TAKAHASHI

IPC: H03F1/52 ,  H03F3/24

Abstract: A clamping circuit is connected between a ground potential and a node through which a radio frequency signal passes. The clamping circuit includes multiple clamping elements that are cascaded. Each of the multiple clamping elements becomes conductive when a voltage greater than or equal to a forward voltage is applied thereto. At least one of the multiple clamping elements is implemented by a resistor-connected transistor that includes a bipolar transistor and a base-collector resistance element connected between the base and the collector of the bipolar transistor.

公开(公告)号：US20250055427A1

公开(公告)日：2025-02-13

申请号：US18932829

申请日：2024-10-31

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Takayuki TSUTSUI ,  Shinnosuke TAKAHASHI

IPC: H03F3/213 ,  H03F1/30

Abstract: A radio frequency amplification circuit includes an amplification transistor, a first transistor, and a Schottky barrier diode. The amplification transistor has a base to which a radio frequency signal is supplied and a collector from which the radio frequency signal amplified is outputted, and is made of a compound semiconductor. The first transistor has a base to which a first bias is supplied, and an emitter electrically coupled to the base of the amplification transistor and configured to supply a second bias to the base of the amplification transistor, and is made of the compound semiconductor. The Schottky barrier diode has an anode electrically coupled to the base of the first transistor and a cathode electrically coupled to the emitter of the first transistor.

公开(公告)号：US20230318543A1

公开(公告)日：2023-10-05

申请号：US18328653

申请日：2023-06-02

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Shigeki KOYA ,  Shaojun MA ,  Shinnosuke TAKAHASHI

IPC: H03F3/21 ,  H01L29/732

CPC classification number: H03F3/21 ,  H01L29/7325 ,  H03F2200/451

Abstract: A power amplifier comprising amplifier circuits of multiple stages. Each of the amplifier circuits of multiple stages includes a bipolar transistor and a base electrode. The bipolar transistor included in each of the amplifier circuits of multiple stages includes a collector layer, a base layer placed on the collector layer, and an emitter mesa placed on part of the region of the base layer. The emitter mesa has a shape elongated in one direction in plan view. The base electrode includes a base main portion arranged in such a manner as to be separated from the emitter mesa with a gap in a direction orthogonal to a lengthwise direction of the emitter mesa in plan view. The base main portion has a shape elongated in a direction parallel to the lengthwise direction of the emitter mesa in plan view and is electrically connected to the base layer.

公开(公告)号：US20210098403A1

公开(公告)日：2021-04-01

申请号：US16994187

申请日：2020-08-14

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Masao KONDO ,  Kenji SASAKI ,  Shigeki KOYA ,  Shinnosuke TAKAHASHI

IPC: H01L23/00

Abstract: Two transistor rows are arranged on or in a substrate. Each of the two transistor rows is configured by a plurality of transistors aligned in a first direction, and the two transistor rows are arranged at an interval in a second direction orthogonal to the first direction. A first wiring is arranged between the two transistor rows when seen from above. The first wiring is connected to collectors or drains of the plurality of transistors in the two transistor rows. The first bump overlaps with the first wiring when seen from above, is arranged between the two transistor rows, and is connected to the first wiring.