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    Adapting Cache Processing Using Phase Libraries and Real Time Simulators
    1.
    发明申请
    Adapting Cache Processing Using Phase Libraries and Real Time Simulators 有权

    公开(公告)号：US20210240630A1

    公开(公告)日：2021-08-05

    申请号：US17234031

    申请日：2021-04-19

    Applicant: NetApp, Inc.

    Inventor： Brian McKean ,  Sai Susarla ,  Ariel Hoffman

    IPC: G06F12/0893 ,  G06F11/34 ,  G06F3/06 ,  G06F30/33

    Abstract: A method, a computing device, and a non-transitory machine-readable medium for modifying cache settings in the array cache are provided. Cache settings are set in an array cache, such that the array cache caches data in an input/output (I/O) stream based on the cache settings, Multiple cache simulators simulate the caching the data from the I/O stream in the array cache using different cache settings in parallel with the array cache. The cache settings in the array cache are replaced with the cache settings from one of the cache simulators based on the determination that the cache simulators increase effectiveness of caching data in the array cache.

    System and method for synchronizing caches after reboot
    2.
    发明授权
    System and method for synchronizing caches after reboot 有权

    公开(公告)号：US09830081B2

    公开(公告)日：2017-11-28

    申请号：US14599353

    申请日：2015-01-16

    Applicant: NetApp, Inc.

    Inventor： Somasundaram Krishnasamy ,  Brian McKean ,  Yanling Qi

    IPC: G06F3/06 ,  G06F12/08 ,  G06F12/0866

    CPC classification number: G06F3/0607 ,  G06F3/061 ,  G06F3/0655 ,  G06F3/067 ,  G06F12/0866 ,  G06F2212/2146

    Abstract: A method and system for synchronizing caches after reboot are described. In a cached environment, a host server stores a cache counter associated with the cache, which can be stored in the cache itself or in another permanent storage device. When data blocks are written to the cache, metadata for each data block is also written to the cache. This metadata includes a block counter based on a value of the cache counter. After a number of data operations are performed in the cache, the value of the cache counter is updated. Then, each data block is selectively updated based on a comparison of the value of the cache counter with a value of the block counter in the metadata for the corresponding data block.

    SYSTEM AND METHOD FOR SYNCHRONIZING CACHES AFTER REBOOT
    4.
    发明申请
    SYSTEM AND METHOD FOR SYNCHRONIZING CACHES AFTER REBOOT 有权
    REBOOT之后同步快照的系统和方法

    公开(公告)号：US20160210055A1

    公开(公告)日：2016-07-21

    申请号：US14599353

    申请日：2015-01-16

    Applicant: NetApp, Inc.

    Inventor： Somasundaram Krishnasamy ,  Brian McKean ,  Yanling Qi

    IPC: G06F3/06 ,  G06F12/08

    CPC classification number: G06F3/0607 ,  G06F3/061 ,  G06F3/0655 ,  G06F3/067 ,  G06F12/0866 ,  G06F2212/2146

    Abstract: A method and system for synchronizing caches after reboot are described. In a cached environment, a host server stores a cache counter associated with the cache, which can be stored in the cache itself or in another permanent storage device. When data blocks are written to the cache, metadata for each data block is also written to the cache. This metadata includes a block counter based on a value of the cache counter. After a number of data operations are performed in the cache, the value of the cache counter is updated. Then, each data block is selectively updated based on a comparison of the value of the cache counter with a value of the block counter in the metadata for the corresponding data block.

    Abstract translation: 描述了重新启动之后同步缓存的方法和系统。 在缓存环境中，主机服务器存储与高速缓存相关联的高速缓存计数器，其可以存储在高速缓存本身或另一永久存储设备中。 当将数据块写入缓存时，每个数据块的元数据也被写入高速缓存。 该元数据包括基于高速缓存计数器的值的块计数器。 在缓存中执行多个数据操作之后，更新缓存计数器的值。 然后，基于高速缓存计数器的值与相应数据块的元数据中的块计数器的值的比较，有选择地更新每个数据块。

    Priority Command Queues for Low Latency Solid State Drives
    5.
    发明申请
    Priority Command Queues for Low Latency Solid State Drives 有权
    低延迟固态硬盘的优先级命令队列

    公开(公告)号：US20140281329A1

    公开(公告)日：2014-09-18

    申请号：US14292399

    申请日：2014-05-30

    Applicant: NetApp, Inc.

    Inventor： Brian McKean ,  Kevin Kidney ,  Jeremy Pinson

    IPC: G06F3/06

    CPC classification number: G06F3/0658 ,  G06F3/0604 ,  G06F3/0611 ,  G06F3/0659 ,  G06F3/0685 ,  G06F3/0688 ,  G06F2003/0697

    Abstract: A method, apparatus, and system of a priority command queues for low latency solid state drives are disclosed. In one embodiment, a system of a storage system includes a command sorter to determine a target storage device for at least one of a solid state drive (SSD) command and a hard disk drive (HDD) command and to place the command in a SSD ready queue if the SSD command is targeted to a SSD storage device of the storage system and to place the HDD command to a HDD ready queue if the HDD command is targeted to an HDD storage device of the storage system, a SSD ready queue to queue the SSD command targeted to the SSD storage device, and a HDD ready queue to queue the HDD command targeted to the HDD storage device.

    Abstract translation: 公开了一种用于低延迟固态驱动器的优先级命令队列的方法，装置和系统。 在一个实施例中，存储系统的系统包括命令分类器，用于为固态驱动器（SSD）命令和硬盘驱动器（HDD）命令中的至少一个确定目标存储设备，并将命令放置在SSD 如果SSD命令被定位到存储系统的SSD存储设备，并且如果HDD命令针对存储系统的HDD存储设备，则将HDD命令放置到HDD就绪队列，准备就绪队列 针对SSD存储设备的SSD命令以及HDD就绪队列来排队指向HDD存储设备的HDD命令。

    Adapting cache processing using phase libraries and real time simulators
    6.
    发明授权
    Adapting cache processing using phase libraries and real time simulators 有权

    公开(公告)号：US11593271B2

    公开(公告)日：2023-02-28

    申请号：US17234031

    申请日：2021-04-19

    Applicant: NetApp, Inc.

    Inventor： Brian McKean ,  Sai Susarla ,  Ariel Hoffman

    IPC: G06F12/0893 ,  G06F3/06 ,  G06F11/34 ,  G06F30/33

    Abstract: A method, a computing device, and a non-transitory machine-readable medium for modifying cache settings in the array cache are provided. Cache settings are set in an array cache, such that the array cache caches data in an input/output (I/O) stream based on the cache settings. Multiple cache simulators simulate the caching the data from the I/O stream in the array cache using different cache settings in parallel with the array cache. The cache settings in the array cache are replaced with the cache settings from one of the cache simulators based on the determination that the cache simulators increase effectiveness of caching data in the array cache.

    System and method for synchronizing caches after reboot
    7.
    发明授权
    System and method for synchronizing caches after reboot 有权

    公开(公告)号：US10831369B2

    公开(公告)日：2020-11-10

    申请号：US15821119

    申请日：2017-11-22

    Applicant: NETAPP, INC.

    Inventor： Somasundaram Krishnasamy ,  Brian McKean ,  Yanling Qi

    IPC: G06F3/06 ,  G06F12/0866

    Abstract: A method and system for synchronizing caches after reboot are described. In a cached environment, a host server stores a cache counter associated with the cache, which can be stored in the cache itself or in another permanent storage device. When data blocks are written to the cache, metadata for each data block is also written to the cache. This metadata includes a block counter based on a value of the cache counter. After a number of data operations are performed in the cache, the value of the cache counter is updated. Then, each data block is selectively updated based on a comparison of the value of the cache counter with a value of the block counter in the metadata for the corresponding data block.

    Storage Controller Caching Using Symmetric Storage Class Memory Devices
    8.
    发明申请
    Storage Controller Caching Using Symmetric Storage Class Memory Devices 审中-公开

    公开(公告)号：US20180165194A1

    公开(公告)日：2018-06-14

    申请号：US15892038

    申请日：2018-02-08

    Applicant: NetApp, Inc.

    Inventor： Brian McKean ,  Gregory Friebus ,  Sandeep Kumar R. Ummadi ,  Pradeep Ganesan

    IPC: G06F12/0804 ,  G06F12/02 ,  G06F12/0868 ,  G06F3/06

    Abstract: Systems and techniques for performing a data transaction are disclosed that provide data redundancy using two or more cache devices. In some embodiments, a data transaction is received by a storage controller of a storage system from a host system. The storage controller caches data and/or metadata associated with the data transaction to at least two cache devices that are discrete from the storage controller. After caching, the storage controller provides a transaction completion response to the host system from which the transaction was received. In some examples, each of the at least two cache devices includes a storage class memory. In some examples, the storage controller caches metadata to the at least two cache devices and to a controller cache of the storage controller, while data is cached to the at least two cache devices without being cached in the controller cache.

    Storage Controller Caching Using Symmetric Storage Class Memory Devices
    9.
    发明申请
    Storage Controller Caching Using Symmetric Storage Class Memory Devices 有权
    存储控制器缓存使用对称存储类存储器件

    公开(公告)号：US20170046259A1

    公开(公告)日：2017-02-16

    申请号：US14826870

    申请日：2015-08-14

    Applicant: NetApp, Inc.

    Inventor： Brian McKean ,  Gregory Friebus ,  Sandeep Kumar R. Ummadi ,  Pradeep Ganesan

    IPC: G06F12/08

    CPC classification number: G06F12/0804 ,  G06F3/06 ,  G06F12/0238 ,  G06F12/0246 ,  G06F12/0868 ,  G06F2212/1021 ,  G06F2212/283 ,  G06F2212/312 ,  G06F2212/608

    Abstract: Systems and techniques for performing a data transaction are disclosed that provide data redundancy using two or more cache devices. In some embodiments, a data transaction is received by a storage controller of a storage system from a host system. The storage controller caches data and/or metadata associated with the data transaction to at least two cache devices that are discrete from the storage controller. After caching, the storage controller provides a transaction completion response to the host system from which the transaction was received. In some examples, each of the at least two cache devices includes a storage class memory. In some examples, the storage controller caches metadata to the at least two cache devices and to a controller cache of the storage controller, while data is cached to the at least two cache devices without being cached in the controller cache.

    Abstract translation: 公开了用于执行数据事务的系统和技术，其使用两个或更多个高速缓存设备来提供数据冗余。 在一些实施例中，存储系统的存储控制器从主机系统接收数据事务。 存储控制器将与数据事务相关联的数据和/或元数据与存储控制器离散的至少两个缓存设备进行高速缓存。 缓存后，存储控制器向收到事务的主机系统提供事务完成响应。 在一些示例中，至少两个缓存设备中的每一个包括存储类存储器。 在一些示例中，存储控制器将元数据缓存到至少两个高速缓存设备和存储控制器的控制器高速缓存，而数据被缓存到至少两个高速缓存设备而不被缓存在控制器高速缓存中。

    Priority command queues for low latency solid state drives
    10.
    发明授权
    Priority command queues for low latency solid state drives 有权
    低延迟固态驱动器的优先级命令队列

    公开(公告)号：US09400615B2

    公开(公告)日：2016-07-26

    申请号：US14292399

    申请日：2014-05-30

    Applicant: NetApp, Inc.

    Inventor： Brian McKean ,  Kevin Kidney ,  Jeremy Pinson

    IPC: G06F3/06

    CPC classification number: G06F3/0658 ,  G06F3/0604 ,  G06F3/0611 ,  G06F3/0659 ,  G06F3/0685 ,  G06F3/0688 ,  G06F2003/0697

    Abstract: A method, apparatus, and system of a priority command queues for low latency solid state drives are disclosed. In one embodiment, a system of a storage system includes a command sorter to determine a target storage device for at least one of a solid state drive (SSD) command and a hard disk drive (HDD) command and to place the command in a SSD ready queue if the SSD command is targeted to a SSD storage device of the storage system and to place the HDD command to a HDD ready queue if the HDD command is targeted to an HDD storage device of the storage system, a SSD ready queue to queue the SSD command targeted to the SSD storage device, and a HDD ready queue to queue the HDD command targeted to the HDD storage device.

    Abstract translation: 公开了一种用于低延迟固态驱动器的优先级命令队列的方法，装置和系统。 在一个实施例中，存储系统的系统包括命令分类器，用于为固态驱动器（SSD）命令和硬盘驱动器（HDD）命令中的至少一个确定目标存储设备，并将命令放置在SSD 如果SSD命令被定位到存储系统的SSD存储设备，并且如果HDD命令针对存储系统的HDD存储设备，则将HDD命令放置到HDD就绪队列，准备就绪队列 针对SSD存储设备的SSD命令以及HDD就绪队列来排队指向HDD存储设备的HDD命令。

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