公开(公告)号：US11979769B2

公开(公告)日：2024-05-07

申请号：US17238457

申请日：2021-04-23

Applicant: Nokia Solutions and Networks Oy

Inventor： Bogdan Uscumlic ,  Andrea Enrici

IPC: H04W28/02 ,  H04L5/00 ,  H04W28/08 ,  H04W28/086

CPC classification number: H04W28/0263 ,  H04L5/0005 ,  H04L5/0098 ,  H04W28/0831 ,  H04W28/0861

Abstract: A programmable device includes a plurality of first partial reconfiguration slots, a plurality of transceivers and a second partial reconfiguration slot. The plurality of first partial reconfiguration slots are configured to execute one or more applications or network functions. The second partial reconfiguration slot is configured to route data traffic flows between the plurality of first partial reconfiguration slots and the plurality of transceivers.

公开(公告)号：US11579894B2

公开(公告)日：2023-02-14

申请号：US17081555

申请日：2020-10-27

Applicant: Nokia Solutions and Networks Oy

Inventor： Andrea Enrici ,  Bogdan Uscumlic

IPC: G06F9/4401 ,  G06F13/40

Abstract: A device includes a plurality of reconfigurable resources, a bus, and a configurator. The bus interconnects the plurality of reconfigurable resources. The configurator is configured to deterministically compute a segmented interconnect configuration for the bus based on operational parameters associated with the device and operational constraints associated with program modules to be executed by the plurality of reconfigurable resources.

公开(公告)号：US12261779B2

公开(公告)日：2025-03-25

申请号：US18525978

申请日：2023-12-01

Applicant: Nokia Solutions and Networks Oy

Inventor： Bogdan Uscumlic ,  Andrea Enrici

IPC: H04L47/22 ,  H04L41/14

Abstract: In some examples, an apparatus for protocol independent deterministic transport of data in a time-sensitive network comprises a processor, a memory coupled to the processor, the memory configured to store program code executable by the processor, the program code comprising one or more instructions, whereby to cause the apparatus to receive synchronisation data from the network, the synchronisation data comprising a measure for a clock frequency supporting transport of deterministic data traffic over the network, receive multiple input packets, the input packets comprising deterministic data traffic and non-deterministic data traffic, and generate, from the multiple input packets and using the synchronisation data, a set of isochronous output packets comprising respective payloads and headers.

公开(公告)号：US11973674B2

公开(公告)日：2024-04-30

申请号：US16990458

申请日：2020-08-11

Applicant: Nokia Solutions and Networks Oy

Inventor： Andrea Enrici ,  Bogdan Uscumlic ,  Julien Lallet

IPC: H04L43/0852 ,  G06F16/901 ,  G06F30/34 ,  H04L47/56 ,  H04L47/74 ,  H04L47/80 ,  H04L47/83

CPC classification number: H04L43/0852 ,  G06F16/9017 ,  G06F30/34 ,  H04L47/56 ,  H04L47/745 ,  H04L47/801 ,  H04L47/805 ,  H04L47/83

Abstract: A method for allocating resources of a field-programmable gate array (FPGA), the method comprising: deterministically estimating a maximum latency for executing a network service at the FPGA; determining that the maximum latency is less than a threshold latency value associated with the network service; outputting an acknowledgement indicating that the maximum latency is less than or equal to the threshold latency value; receiving confirmation that the FPGA has been selected to execute the network service within a threshold time period; and deterministically scheduling the resources of the FPGA for executing the network service in response to receiving the confirmation within the threshold time period.

公开(公告)号：US20240195742A1

公开(公告)日：2024-06-13

申请号：US18063346

申请日：2022-12-08

Applicant: Nokia Solutions and Networks Oy

Inventor： Andrea Enrici

IPC: H04L47/12 ,  H04L45/02 ,  H04L47/30

CPC classification number: H04L47/12 ,  H04L45/02 ,  H04L47/30

Abstract: Example embodiments disclose a method for avoiding deadlock in a network includes generating a finite state machine indicating possible routing decisions of incoming packets for a plurality of switches, analyzing the finite state machine, determining at least one memory overflow state based on the analyzing, generating at least one anti-deadlock rule in response to determining the at least one memory overflow state, and transmitting the at least one anti-deadlock rule to the plurality of switches.

公开(公告)号：US11416399B2

公开(公告)日：2022-08-16

申请号：US16911680

申请日：2020-06-25

Applicant: Nokia Solutions and Networks Oy

Inventor： Andrea Enrici ,  Bogdan Uscumlic

IPC: G06F12/0806

Abstract: A server includes a field programmable gate array (FPGA) partitioned into a set of partial reconfiguration (PR) slots and a memory that supports a set of logical buffers. A deterministic application request module (DARM) receives application requests to allocate the set of reconfiguration slots to one or more tenants and the one or more tenants configure the allocated reconfiguration slot to perform tasks. The DARM stores data associated with the application request in a first logical buffer from the set of logical buffers. A reconfiguration slot scheduling (RSS) module identifies a first reconfiguration slot from the set of reconfiguration slots and associates the first reconfiguration slot with the first logical buffer. A reconfiguration slot initialization (RSI) module reconfigures the first reconfiguration slot to perform the tasks based on the data stored in the first logical buffer.

公开(公告)号：US12164426B2

公开(公告)日：2024-12-10

申请号：US18329277

申请日：2023-06-05

Applicant: Nokia Solutions and Networks Oy

Inventor： Andrea Enrici ,  Julien Lallet

IPC: G06F12/0811 ,  G06F12/0804 ,  G06F12/0813 ,  G06F12/0871 ,  G06F13/16

Abstract: A network-based apparatus includes at least one processor and at least one memory including computer program code. The at least one memory and the computer program code are configured to, with the at least one processor, cause the network apparatus to configure a cache manager according to a cache management policy identified in a request from a network orchestrator, the cache manager managing a cache of a multi-level cache hierarchy, the cache storing bitstreams for configuring a programmable device.

公开(公告)号：US12081636B2

公开(公告)日：2024-09-03

申请号：US17239822

申请日：2021-04-26

Applicant: Nokia Solutions and Networks Oy

Inventor： Andrea Enrici

IPC: H04L67/60 ,  G06F16/901 ,  H04L41/12

CPC classification number: H04L67/60 ,  G06F16/9024 ,  G06F16/9027 ,  H04L41/12

Abstract: A network device includes processing circuitry configured to cause the network device to: partition a flow graph for an application to generate a partitioned graph of nodes and edges, each of the nodes including computations mapped to an execution unit to execute at least a portion of the application, and each of the edges denoting communications between execution units; determine whether the partitioned graph is an irreducible graph; and schedule the computations and the communications for execution in response to determining that the partitioned graph is an irreducible graph.

公开(公告)号：US11669452B2

公开(公告)日：2023-06-06

申请号：US17095109

申请日：2020-11-11

Applicant: Nokia Solutions and Networks Oy

Inventor： Andrea Enrici ,  Julien Lallet

IPC: G06F12/0811 ,  G06F12/0804 ,  G06F12/0813 ,  G06F12/0871 ,  G06F13/16

CPC classification number: G06F12/0811 ,  G06F12/0804 ,  G06F12/0813 ,  G06F12/0871 ,  G06F13/1668

Abstract: A network-based apparatus includes at least one processor and at least one memory including computer program code. The at least one memory and the computer program code are configured to, with the at least one processor, cause the network apparatus to configure a cache manager according to a cache management policy identified in a request from a network orchestrator, the cache manager managing a cache of a multi-level cache hierarchy, the cache storing bitstreams for configuring a programmable device.

公开(公告)号：US11645120B2

公开(公告)日：2023-05-09

申请号：US17171256

申请日：2021-02-09

Applicant: Nokia Solutions and Networks Oy

Inventor： Andrea Enrici

IPC: G06F9/50

CPC classification number: G06F9/5038 ,  G06F9/5016

Abstract: A network device, including processing circuitry configured to determine a depth first search tree (DFST) based on a dependency graph included in a request to allocate memory bandwidth to a set of tasks, determine a set of groups of edges and nodes in the dependency graph based on the DFST, and allocate the memory bandwidth to the set of tasks by allocating the memory bandwidth to edges included in the set of groups of edges and nodes.