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公开(公告)号：US06878582B2
公开(公告)日：2005-04-12
申请号：US10876873
申请日：2004-06-25
IPC分类号： H01L21/265 , H01L21/28 , H01L21/336 , H01L29/49 , H01L29/78 , H01L21/8238
CPC分类号： H01L29/4983 , H01L21/26586 , H01L21/28105 , H01L29/66484 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7831 , H01L29/7836 , Y10S257/90
摘要： A low-GIDL current MOSFET device structure and a method of fabrication thereof which provides a low-GIDL current. The MOSFET device structure contains a central gate conductor whose edges may slightly overlap the source/drain diffusions, and left and right side wing gate conductors which are separated from the central gate conductor by a thin insulating and diffusion barrier layer.
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公开(公告)号：US06806534B2
公开(公告)日：2004-10-19
申请号：US10342423
申请日：2003-01-14
IPC分类号： H01L2976
CPC分类号： H01L29/66583 , H01L21/26586 , H01L21/28114 , H01L29/665 , H01L29/66553
摘要： A MOSFET fabrication methodology and device structure, exhibiting improved gate activation characteristics. The gate doping that may be introduced while the source drain regions are protected by a damascene mandrel to allow for a very high doping in the gate conductors, without excessively forming deep source/drain diffusions. The high gate conductor doping minimizes the effects of electrical depletion of carriers in the gate conductor. The MOSFET fabrication methodology and device structure further results in a device having a lower gate conductor width less than the minimum lithographic minimum image, and a wider upper gate conductor portion width which may be greater than the minimum lithographic image. Since the effective channel length of the MOSFET is defined by the length of the lower gate portion, and the line resistance is determined by the width of the upper gate portion, both short channel performance and low gate resistance are satisfied simultaneously.
摘要翻译： MOSFET制造方法和器件结构，表现出改进的栅极激活特性。 当源极漏极区域被镶嵌心轴保护以允许栅极导体中的非常高的掺杂而不会过度地形成深的源极/漏极扩散时，可以引入栅极掺杂。 高栅极导体掺杂最大限度地减小了栅极导体中载流子的电耗损的影响。 MOSFET制造方法和器件结构进一步导致具有小于最小光刻最小图像的较低栅极导体宽度的器件，以及可能大于最小光刻图像的较宽上部栅极导体部分宽度。 由于MOSFET的有效沟道长度由下栅极部分的长度限定，并且线路电阻由上部栅极部分的宽度决定，所以同时满足短沟道性能和低栅极电阻。
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公开(公告)号：US06841826B2
公开(公告)日：2005-01-11
申请号：US10345472
申请日：2003-01-15
IPC分类号： H01L21/265 , H01L21/28 , H01L21/336 , H01L29/49 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/062
CPC分类号： H01L29/4983 , H01L21/26586 , H01L21/28105 , H01L29/66484 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7831 , H01L29/7836 , Y10S257/90
摘要： A low-GIDL current MOSFET device structure and a method of fabrication thereof which provides a low-GIDL current. The MOSFET device structure contains a central gate conductor whose edges may slightly overlap the source/drain diffusions, and left and right side wing gate conductors which are separated from the central gate conductor by a thin insulating and diffusion barrier layer.
摘要翻译： 低GIDL电流MOSFET器件结构及其制造方法，其提供低GIDL电流。 MOSFET器件结构包含中心栅极导体，其边缘可能与源极/漏极扩散稍微重叠，以及通过薄的绝缘和扩散阻挡层与中心栅极导体分离的左侧和右侧翼栅极导体。
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公开(公告)号：US06780694B2
公开(公告)日：2004-08-24
申请号：US10338930
申请日：2003-01-08
IPC分类号： H01L21338
CPC分类号： H01L21/28114 , H01L21/26586 , H01L21/82385 , H01L21/823864 , H01L29/42376 , H01L29/665
摘要： A method of fabricating a semiconductor transistor device comprises the steps as follows. Provide a semiconductor substrate with a gate dielectric layer thereover and a lower gate electrode structure formed over the gate dielectric layer with the lower gate electrode structure having a lower gate top. Form a planarizing layer over the gate dielectric layer leaving the gate top of the lower gate electrode structure exposed. Form an upper gate structure over the lower gate electrode structure to form a T-shaped gate electrode with an exposed lower surface of the upper gate surface and exposed vertical sidewalls of the gate electrode. Remove the planarizing layer. Form source/drain extensions in the substrate protected from the short channel effect. Form sidewall spacers adjacent to the exposed lower surface of the upper gate and the exposed vertical sidewalls of the T-shaped gate electrode. Form source/drain regions in the substrate. Form silicide layers on top of the T-shaped gate electrode and above the source/drain regions.
摘要翻译： 制造半导体晶体管器件的方法包括以下步骤。 提供其上具有栅极介电层的半导体衬底和形成在栅极电介质层上的下部栅极电极结构，而下部栅电极结构具有较低的栅极顶部。 在栅极电介质层上形成平坦化层，离开下部栅电极结构的栅极顶部。 在下栅极电极结构上形成上栅极结构，形成具有上栅极表面的暴露下表面和暴露的栅电极垂直侧壁的T形栅电极。 取出平坦化层。 衬底中形成源/漏极扩展，防止短沟道效应。 形成邻近上部栅极的暴露的下表面和T形栅电极的暴露的垂直侧壁的侧壁间隔物。 在衬底中形成源/漏区。 在T形栅电极的顶部和源极/漏极区之上形成硅化物层。
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公开(公告)号：US07732288B2
公开(公告)日：2010-06-08
申请号：US12367764
申请日：2009-02-09
申请人： Huilong Zhu , Lawrence A. Clevenger , Omer H. Dokumaci , Oleg Gluschenkov , Kaushik A. Kumar , Carl J. Radens , Dureseti Chidambarrao
发明人： Huilong Zhu , Lawrence A. Clevenger , Omer H. Dokumaci , Oleg Gluschenkov , Kaushik A. Kumar , Carl J. Radens , Dureseti Chidambarrao
IPC分类号： H01L29/76 , H01L31/062
CPC分类号： H01L29/0843 , H01L21/26506 , H01L21/26586 , H01L29/6653 , H01L29/66628 , H01L29/66636 , H01L29/7834
摘要： A method for fabricating a semiconductor structure. The novel transistor structure comprises first and second source/drain (S/D) regions whose top surfaces are lower than a top surface of the channel region of the transistor structure. A semiconductor layer and a gate stack on the semiconductor layer are provided. The semiconductor layer includes (i) a channel region directly beneath the gate stack, and (ii) first and second semiconductor regions essentially not covered by the gate stack, and wherein the channel region is disposed between the first and second semiconductor regions. The first and second semiconductor regions are removed. Regions directly beneath the removed first and second semiconductor regions are removed so as to form first and second source/drain regions, respectively, such that top surfaces of the first and second source/drain regions are below a top surface of the channel region.
摘要翻译： 一种半导体结构的制造方法。 新颖的晶体管结构包括顶表面低于晶体管结构的沟道区的顶表面的第一和第二源极/漏极（S / D）区域。 提供半导体层上的半导体层和栅极堆叠。 半导体层包括（i）栅极叠层正下方的沟道区，以及（ii）基本上不被栅极叠层覆盖的第一和第二半导体区，并且其中沟道区设置在第一和第二半导体区之间。 去除第一和第二半导体区域。 除去去除的第一和第二半导体区域正下方的区域，以便分别形成第一和第二源极/漏极区域，使得第一和第二源极/漏极区域的顶表面在通道区域的顶表面之下。
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公开(公告)号：US20090142894A1
公开(公告)日：2009-06-04
申请号：US12367764
申请日：2009-02-09
申请人： Huilong Zhu , Lawrence A. Clevenger , Omer H. Dokumaci , Oleg Gluschenkov , Kaushik A. Kumar , Carl J. Radens , Dureseti Chidambarrao
发明人： Huilong Zhu , Lawrence A. Clevenger , Omer H. Dokumaci , Oleg Gluschenkov , Kaushik A. Kumar , Carl J. Radens , Dureseti Chidambarrao
IPC分类号： H01L21/336
CPC分类号： H01L29/0843 , H01L21/26506 , H01L21/26586 , H01L29/6653 , H01L29/66628 , H01L29/66636 , H01L29/7834
摘要： A method for fabricating a semiconductor structure. The novel transistor structure comprises first and second source/drain (S/D) regions whose top surfaces are lower than a top surface of the channel region of the transistor structure. A semiconductor layer and a gate stack on the semiconductor layer are provided. The semiconductor layer includes (i) a channel region directly beneath the gate stack, and (ii) first and second semiconductor regions essentially not covered by the gate stack, and wherein the channel region is disposed between the first and second semiconductor regions. The first and second semiconductor regions are removed. Regions directly beneath the removed first and second semiconductor regions are removed so as to form first and second source/drain regions, respectively, such that top surfaces of the first and second source/drain regions are below a top surface of the channel region.
摘要翻译： 一种半导体结构的制造方法。 新颖的晶体管结构包括顶表面低于晶体管结构的沟道区的顶表面的第一和第二源极/漏极（S / D）区域。 提供半导体层上的半导体层和栅极堆叠。 半导体层包括（i）栅极叠层正下方的沟道区，以及（ii）基本上不被栅极叠层覆盖的第一和第二半导体区，并且其中沟道区设置在第一和第二半导体区之间。 去除第一和第二半导体区域。 除去去除的第一和第二半导体区域正下方的区域，以便分别形成第一和第二源极/漏极区域，使得第一和第二源极/漏极区域的顶表面在通道区域的顶表面之下。
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7.发明授权Structure and method to improve channel mobility by gate electrode stress modification 有权通过栅电极应力改变来提高沟道迁移率的结构和方法公开(公告)号：US06977194B2
公开(公告)日：2005-12-20
申请号：US10695752
申请日：2003-10-30
申请人： Michael P. Belyansky , Dureseti Chidambarrao , Omer H. Dokumaci , Bruce B. Doris , Oleg Gluschenkov
发明人： Michael P. Belyansky , Dureseti Chidambarrao , Omer H. Dokumaci , Bruce B. Doris , Oleg Gluschenkov
IPC分类号： H01L21/20 , H01L21/28 , H01L21/302 , H01L21/336 , H01L21/44 , H01L21/461 , H01L21/4763 , H01L21/8238 , H01L27/092 , H01L29/49 , H01L29/72 , H01L29/78 , H01L29/786 , H01L31/062
CPC分类号： H01L29/7845 , H01L21/823807 , H01L21/823835 , H01L21/823842 , H01L29/4908 , H01L29/66795 , H01L29/785
摘要： In producing complementary sets of metal-oxide-semiconductor (CMOS) field effect transistors, including nFET and pFET), carrier mobility is enhanced or otherwise regulated through the reacting the material of the gate electrode with a metal to produce a stressed alloy (preferably CoSi2, NiSi, or PdSi) within a transistor gate. In the case of both the nFET and pFET, the inherent stress of the respective alloy results in an opposite stress on the channel of respective transistor. By maintaining opposite stresses in the nFET and pFET alloys or silicides, both types of transistors on a single chip or substrate can achieve an enhanced carrier mobility, thereby improving the performance of CMOS devices and integrated circuits.
摘要翻译： 在制造包括nFET和pFET的互补金属氧化物半导体（CMOS）场效应晶体管的情况下，通过使栅电极的材料与金属反应来增强或调节载流子迁移率，以产生应力合金（优选CoSi 2Si，NiSi或PdSi）。 在nFET和pFET两者的情况下，各合金的固有应力对相应晶体管的沟道产生相反的应力。 通过在nFET和pFET合金或硅化物中保持相反的应力，单个芯片或衬底上的两种类型的晶体管可以实现增强的载流子迁移率，从而提高CMOS器件和集成电路的性能。
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8.发明授权Method for differential oxidation rate reduction for n-type and p-type materials 失效n型和p型材料差示氧化速率降低的方法公开(公告)号：US06667197B1
公开(公告)日：2003-12-23
申请号：US10314499
申请日：2002-12-06
IPC分类号： H01L2100
CPC分类号： H01L21/823842 , H01L21/823864
摘要： A method of forming a substantially uniform oxide film over surfaces with different level of doping and/or different dopant type is disclosed. In one aspect, a method for forming a uniform oxide spacer on the sidewalls of heavily doped n- and p-type gates is disclosed. The method includes providing a semiconductor substrate having at least two regions with dissimilar dopant characteristics, optionally heating the substrate; and forming a uniform oxide layer over the at least two regions by exposing the substrate to a gaseous mixture including atomic oxygen.
摘要翻译： 公开了在具有不同掺杂水平和/或不同掺杂剂类型的表面上形成基本上均匀的氧化膜的方法。 一方面，公开了在重掺杂的n型和p型栅极的侧壁上形成均匀的氧化物间隔物的方法。 该方法包括提供具有至少两个具有不同掺杂特性的区域的半导体衬底，可选地加热衬底; 以及通过将所述衬底暴露于包括原子氧的气体混合物，在所述至少两个区域上形成均匀的氧化物层。
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公开(公告)号：US07374987B2
公开(公告)日：2008-05-20
申请号：US10935136
申请日：2004-09-07
IPC分类号： H01L21/336
CPC分类号： H01L29/6656 , H01L21/823807 , H01L21/823864 , H01L21/84 , H01L27/1203 , H01L29/42316 , H01L29/7842 , H01L29/7843 , H01L29/808
摘要： A substrate under tension and/or compression improves performance of devices fabricated therein. Tension and/or compression can be imposed on a substrate through selection of appropriate gate sidewall spacer material disposed above a device channel region wherein the spacers are formed adjacent both the gate and the substrate and impose forces on adjacent substrate areas. Another embodiment comprises compressive stresses imposed in the plane of the channel using SOI sidewall spacers made of polysilicon that is expanded by oxidation. The substrate areas under compression or tension exhibit charge mobility characteristics different from those of a non-stressed substrate. By controllably varying these stresses within NFET and PFET devices formed on a substrate, improvements in IC performance have been demonstrated.
摘要翻译： 在张力和/或压缩下的基底改善了在其中制造的器件的性能。 可以通过选择设置在器件沟道区域上方的适当的栅极侧壁间隔物施加张力和/或压缩，其中间隔物邻近栅极和衬底形成，并且在邻近衬底区域上施加力。 另一个实施例包括使用通过氧化扩展的多晶硅制成的SOI侧壁间隔施加在沟道的平面中的压应力。 在压缩或张力下的衬底区域表现出不同于非应力衬底的电荷迁移率特性。 通过可控地改变在衬底上形成的NFET和PFET器件内的这些应力，已经证明了IC性能的提高。
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公开(公告)号：US06974981B2
公开(公告)日：2005-12-13
申请号：US10318600
申请日：2002-12-12
IPC分类号： H01L21/76 , H01L21/762 , H01L21/8238 , H01L29/80 , H01L31/109 , H01L31/112 , H01L29/774
CPC分类号： H01L29/7846 , H01L21/76232 , H01L21/823807 , H01L21/823878 , H01L29/785
摘要： A substrate under tension and/or compression improves performance of devices fabricated therein. Tension and/or compression can be imposed on a substrate through selection of appropriate STI fill material. The STI regions are formed in the substrate layer and impose forces on adjacent substrate areas. The substrate areas under compression or tension exhibit charge mobility characteristics different from those of a non-stressed substrate. By controllably varying these stresses within NFET and PFET devices formed on a substrate, improvements in IC performance are achieved.
摘要翻译： 在张力和/或压缩下的基底改善了在其中制造的器件的性能。 可以通过选择适当的STI填充材料将张力和/或压缩施加在基底上。 STI区域形成在衬底层中并且在相邻衬底区域上施加力。 在压缩或张力下的衬底区域表现出不同于非应力衬底的电荷迁移率特性。 通过可控地改变在衬底上形成的NFET和PFET器件内的这些应力，实现了IC性能的提高。
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