公开(公告)号：US09030403B2

公开(公告)日：2015-05-12

申请号：US13650155

申请日：2012-10-12

Applicant: Pixtronix, Inc.

Inventor： Hajime Akimoto ,  Toshio Miyazawa

IPC: G09G5/00

CPC classification number: G09G5/00 ,  G09G3/2022 ,  G09G3/3433 ,  G09G2300/0473 ,  G09G2300/0809 ,  G09G2300/0823 ,  G09G2300/0842 ,  G09G2300/0866 ,  G09G2300/0876 ,  G09G2310/0262

Abstract: A pixel circuit includes a first control electrode and a second control electrode between which a mechanical shutter is put, and a first control voltage application circuit for inputting a first control voltage to the first control electrode according to an image signal. The first control voltage application circuit includes an input transistor, a retaining capacitor and a first transistor. One of current terminals of the input transistor is connected to a signal line. A gate of the input transistor is connected to a scanning line. One terminal of the retaining capacitor is input with a capacitor control signal and the other terminal is connected to the input transistor. The first transistor has a gate connected to the retaining capacitor and two current terminals, one of which is connected to a first control electrode and the other of which is input with a first control signal.

Abstract translation: 像素电路包括第一控制电极和放置机械快门的第二控制电极，以及根据图像信号将第一控制电压输入到第一控制电极的第一控制电压施加电路。 第一控制电压施加电路包括输入晶体管，保持电容和第一晶体管。 输入晶体管的一个电流端子连接到信号线。 输入晶体管的栅极连接到扫描线。 保持电容器的一个端子输入电容器控制信号，另一个端子连接到输入晶体管。 第一晶体管具有连接到保持电容器的栅极和两个电流端子，其中一个连接到第一控制电极，另一个被输入第一控制信号。

公开(公告)号：US09099997B2

公开(公告)日：2015-08-04

申请号：US13651785

申请日：2012-10-15

Applicant: Pixtronix, Inc.

Inventor： Toshio Miyazawa ,  Hajime Akimoto

IPC: H03K3/356 ,  G09G3/34

CPC classification number: H03K5/153 ,  G09G3/2092 ,  G09G3/3433 ,  G09G2310/02 ,  G09G2310/0264 ,  G09G2310/0289 ,  G09G2310/0294 ,  G09G2310/08 ,  G09G2320/045 ,  H03K3/356113 ,  H03K2005/00078 ,  H03K2005/00215

Abstract: A latch circuit which can control a drain avalanche effect and improve reliability is provided. The latch circuit includes an input transistor importing a voltage corresponding to “0” or “1” when the scanning voltage is input to a gate, a storage capacitance storing a voltage imported by the input transistor, and having a first electrode and a second electrode, the first electrode is input with a capacitance control signal and the second electrode is connected to a second electrode of the input transistor, a first conduction type first transistor having a gate connected to the second electrode of the input transistor, a second electrode connected to a first output terminal, and a first electrode input with a first latch control signal, and a second conduction type second transistor having a gate connected to the second electrode of the first transistor, a second electrode connected to a second output terminal, and a first electrode input with a second latch control signal.

Abstract translation: 提供一种能够控制排水雪崩效应并提高可靠性的锁存电路。 锁存电路包括输入晶体管，当扫描电压输入到栅极时，输入对应于“0”或“1”的电压，存储由输入晶体管引入的电压的存储电容，并具有第一电极和第二电极 第一电极被输入电容控制信号，第二电极连接到输入晶体管的第二电极，第一导电型第一晶体管具有连接到输入晶体管的第二电极的栅极，第二电极连接到 第一输出端子和具有第一锁存器控制信号的第一电极输入端和连接到第一晶体管的第二电极的栅极的第二导电型第二晶体管，连接到第二输出端子的第二电极和第一 电极输入具有第二锁存控制信号。

公开(公告)号：US09013523B2

公开(公告)日：2015-04-21

申请号：US14278373

申请日：2014-05-15

Applicant: Pixtronix, Inc.

Inventor： Kenta Kajiyama ,  Hajime Akimoto

IPC: G09G5/10 ,  G09G5/00 ,  G09G3/20

CPC classification number: G09G3/2003 ,  G09G3/2022 ,  G09G2310/0235 ,  G09G2310/024 ,  G09G2320/0242 ,  G09G2320/0261 ,  G09G2320/0266 ,  G09G2340/06

Abstract: Provided are a display device that can suppress occurrence of a color breakup as well as occurrence of a false contour, and a control method therefor. In the display device, a plurality of sub-frame periods forming one frame period are divided into a first group to which sub-frame periods with the same length of light transmission periods belong; and a second group to which sub-frame periods with lengths of light transmission periods shorter than those of the sub-frame periods in the first group and different from each other belong. Further, among the sub-frame periods that belong to the first group, sub-frame periods having the light transmission period increase in number from a middle of the one frame period toward a start point and an endpoint of the one frame period in accordance with an increase of the gray level.

Abstract translation: 提供了能够抑制颜色分解的发生以及假轮廓的发生的显示装置及其控制方法。 在显示装置中，形成一个帧周期的多个子帧周期被划分成具有相同长度的光传输周期所属的子帧周期的第一组; 以及第二组，其中具有比第一组中的子帧周期短的光发送周期的长度的子帧周期属于彼此不同的子帧周期。 此外，在属于第一组的子帧周期中，具有从一个帧周期的中间到开始点的光发送周期的子帧周期数量增加，并且一帧周期的端点根据 增加了灰度级。

公开(公告)号：US09235999B2

公开(公告)日：2016-01-12

申请号：US13726279

申请日：2012-12-24

Applicant: Pixtronix, Inc.

Inventor： Hajime Akimoto ,  Takahiko Muneyoshi ,  Kenta Kajiyama

IPC: G09G1/00 ,  G09G3/34 ,  G02B26/02 ,  G02B26/08

CPC classification number: G09G1/005 ,  G02B26/023 ,  G02B26/0841 ,  G09G3/3433 ,  G09G2300/08 ,  G09G2300/0857 ,  G09G2310/06

Abstract: A display device includes a plurality of pixels each including a mechanical shutter. The display device electrically controls the position of the mechanical shutter to provide image display. Each of the pixels includes a pixel circuit for electrically controlling the position of the mechanical shutter. The pixel circuit includes a first control electrode and a second control electrode provided as a pair with respect to the mechanical shutter; a first mean for applying a prescribed control voltage to the first control electrode and the second control electrode to put the mechanical shutter and the first control electrode or the second control electrode into contact with each other; and a second mean for, in a state where the mechanical shutter is at a stop, decreasing a potential difference between the mechanical shutter and the first control electrode or the second control electrode which is in contact with the mechanical shutter.

Abstract translation: 显示装置包括多个像素，每个像素包括机械快门。 显示装置电气地控制机械快门的位置以提供图像显示。 每个像素包括用于电控制机械快门的位置的像素电路。 像素电路包括相对于机械快门设置成一对的第一控制电极和第二控制电极; 将规定的控制电压施加到第一控制电极和第二控制电极以使机械快门和第一控制电极或第二控制电极彼此接触的第一意图; 并且在机械快门处于停止状态的第二平均值是减小机械快门和与机械快门接触的第一控制电极或第二控制电极之间的电位差。

公开(公告)号：US20150295568A1

公开(公告)日：2015-10-15

申请号：US14752361

申请日：2015-06-26

Applicant: Pixtronix, Inc.

Inventor： Toshio Miyazawa ,  Hajime Akimoto

IPC: H03K5/153 ,  G09G3/34 ,  G09G3/20

CPC classification number: H03K5/153 ,  G09G3/2092 ,  G09G3/3433 ,  G09G2310/02 ,  G09G2310/0264 ,  G09G2310/0289 ,  G09G2310/0294 ,  G09G2310/08 ,  G09G2320/045 ,  H03K3/356113 ,  H03K2005/00078 ,  H03K2005/00215

Abstract: A latch circuit which can control a drain avalanche effect and improve reliability is provided. The latch circuit includes an input transistor importing a voltage corresponding to “0” or “1” when the scanning voltage is input to a gate, a storage capacitance storing a voltage imported by the input transistor, and having a first electrode and a second electrode, the first electrode is input with a capacitance control signal and the second electrode is connected to a second electrode of the input transistor, a first conduction type first transistor having a gate connected to the second electrode of the input transistor, a second electrode connected to a first output terminal, and a first electrode input with a first latch control signal, and a second conduction type second transistor having a gate connected to the second electrode of the first transistor, a second electrode connected to a second output terminal, and a first electrode input with a second latch control signal.

Abstract translation: 提供一种能够控制排水雪崩效应并提高可靠性的锁存电路。 锁存电路包括输入晶体管，当扫描电压输入到栅极时，输入对应于“0”或“1”的电压，存储由输入晶体管引入的电压的存储电容，并具有第一电极和第二电极 第一电极被输入电容控制信号，第二电极连接到输入晶体管的第二电极，第一导电型第一晶体管具有连接到输入晶体管的第二电极的栅极，第二电极连接到 第一输出端子和具有第一锁存器控制信号的第一电极输入端和连接到第一晶体管的第二电极的栅极的第二导电型第二晶体管，连接到第二输出端子的第二电极和第一 电极输入具有第二锁存控制信号。