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公开(公告)号：US11968288B2
公开(公告)日：2024-04-23
申请号：US17659469
申请日：2022-04-15
Applicant: QUALCOMM Incorporated
Inventor： Lennart Karl-Axel Mathe , Brian Clarke Banister , Christos Komninakis , Minkui Liu
CPC classification number: H04L7/0079 , H03M1/1245 , H04W56/005
Abstract: An analog-to-digital converter (ADC) has been disclosed. In some implementations, the ADC is configured to generate ADC samples based on input signals and an ADC input clock. The ADC is further configured to generate at a first time point a synchronized start signal indicating a starting point of capturing the ADC samples. The start signal and a system clock can be synchronized at a second time point. At a third time point, a capturing sample clock for capturing the ADC samples is generated. The synchronized start signal and the capturing sample clock can be input to a counter to determine a time difference between the second and third time points. An ADC output timing of the ADC samples can be determined based on the time difference.
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公开(公告)号：US20140213208A1
公开(公告)日：2014-07-31
申请号：US13752159
申请日：2013-01-28
Applicant: QUALCOMM INCORPORATED
Inventor： Song S. Shi , Lennart Karl-Axel Mathe , Liang Dai
CPC classification number: H04B15/00 , G05F1/10 , H02M1/12 , H02M1/44 , H02M3/156 , H03F1/0211 , H03F3/217 , H03F2200/432
Abstract: Techniques for creating one or more notch frequencies in the power density spectrum of an output voltage generated by switching circuitry. In an aspect, high- and low-side switches are coupled to an output voltage via an inductor. The spectral power of the output voltage at one or more frequencies is estimated, and the estimated spectral power is provided to a switch controller controlling the switches. The switch controller may be configured to switch the switches only in response to detecting that the estimated spectral power at the notch frequency is at a minimum. In certain exemplary aspects, the techniques may be incorporated in an envelope-tracking system, wherein the switching circuitry forms part of a switched-mode power supply (SMPS) supplying low-frequency power to a power amplifier load.
Abstract translation: 在由开关电路产生的输出电压的功率密度谱中产生一个或多个陷波频率的技术。 在一个方面，高侧和低侧开关通过电感耦合到输出电压。 估计在一个或多个频率处的输出电压的频谱功率，并且将估计的频谱功率提供给控制开关的开关控制器。 开关控制器可以被配置为仅响应于检测到陷波频率处的估计频谱功率为最小而切换开关。 在某些示例性方面，这些技术可以并入包络跟踪系统中，其中开关电路形成向功率放大器负载提供低频功率的开关模式电源（SMPS）的一部分。
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公开(公告)号：US20140210550A1
公开(公告)日：2014-07-31
申请号：US13752241
申请日：2013-01-28
Applicant: QUALCOMM INCORPORATED
Inventor： Lennart Karl-Axel Mathe , Joseph D. Rutkowski , Song S. Shi
IPC: H03G1/00
CPC classification number: H03G1/0005 , H03F1/0238
Abstract: Techniques for preventing reverse current in applications wherein a tracking supply voltage is placed in parallel with a switching power stage. The tracking supply voltage may be boosted to a level higher than a battery supply voltage using, e.g., a boost converter. In an aspect, a negative current detection block is provided to detect negative current flow from the boosted tracking supply voltage to the battery supply voltage. A high-side switch of the switching power stage may be disabled in response to detecting the negative current. To prevent false tripping, the tracking supply voltage may be further compared with the battery supply voltage, and a latch may be provided to further control the high-side switch.
Abstract translation: 在跟踪电源电压与开关功率级并联放置的应用中用于防止反向电流的技术。 使用例如升压转换器，跟踪电源电压可以升高到高于电池电源电压的电平。 在一方面，提供负电流检测块以检测从升压的跟踪电源电压到电池电源电压的负电流。 可以响应于检测到负电流而禁用开关功率级的高侧开关。 为了防止错误跳闸，可以将跟踪电源电压进一步与电池电源电压进行比较，并且可以提供锁存器以进一步控制高侧开关。
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公开(公告)号：US20140210433A1
公开(公告)日：2014-07-31
申请号：US13752197
申请日：2013-01-28
Applicant: QUALCOMM INCORPORATED
Inventor： Joseph D Rutkowski , Lennart Karl-Axel Mathe
IPC: G05F1/618
CPC classification number: G05F1/618 , H02M3/156 , H02M3/1563 , H02M2001/0009
Abstract: Techniques for providing negative current information to a control loop for a buck converter in reverse boost mode. In an aspect, negative as well as positive current through an inductor is sensed and provided to adjust a ramp voltage in the control loop for the buck converter. The techniques may prevent current through the inductor during reverse boost mode from becoming increasingly negative without bound; the techniques thereby reduce settling times when the target output voltage is reduced from a first level to a second level. In an aspect, the negative current sensing may be provided by sensing negative current through a charging, or PMOS, switch of the buck converter. The sensed negative current may be subtracted from a current used to generate the ramp voltage.
Abstract translation: 用于以反向升压模式向降压转换器的控制回路提供负电流信息的技术。 在一个方面，检测并提供通过电感器的负电流和正电流以调整用于降压转换器的控制回路中的斜坡电压。 这些技术可以防止在反向升压模式期间通过电感器的电流在没有限制的情况下变得越来越负; 因此当目标输出电压从第一电平降低到第二电平时，这些技术可以减少稳定时间。 在一方面，负电流感测可以通过感测通过降压转换器的充电或PMOS开关的负电流来提供。 感测到的负电流可以从用于产生斜坡电压的电流中减去。
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公开(公告)号：US20140197814A1
公开(公告)日：2014-07-17
申请号：US13740062
申请日：2013-01-11
Applicant: QUALCOMM INCORPORATED
Inventor： Song S. Shi , Pengfei Li , Lennart Karl-Axel Mathe , Yunfei Shi
IPC: G05F3/02
CPC classification number: G05F3/02 , H02M3/155 , H02M3/1582 , H02M2001/008 , H03F1/0238
Abstract: Techniques for generating a boost clock signal for a boost converter from a buck converter clock signal, wherein the boost clock signal has a limited frequency range. In an aspect, the boost clock signal has a maximum frequency determined by Vbst/T, wherein Vbst represents the difference between a target output voltage and a battery voltage, and T represents a predetermined cycle duration. The boost converter may include a pulse insertion block to limit the minimum frequency of the boost clock signal, and a dynamic blanking/delay block to limit the maximum frequency of the boost clock signal. Further techniques are disclosed for generally implementing the minimum frequency limiting and maximum frequency limiting blocks.
Abstract translation: 用于从降压转换器时钟信号产生用于升压转换器的升压时钟信号的技术，其中所述升压时钟信号具有有限的频率范围。 在一方面，升压时钟信号具有由Vbst / T确定的最大频率，其中Vbst表示目标输出电压和电池电压之间的差，T表示预定的周期持续时间。 升压转换器可以包括用于限制升压时钟信号的最小频率的脉冲插入块以及限制升压时钟信号的最大频率的动态消隐/延迟模块。 公开了通常实现最小频率限制和最大频率限制块的其它技术。
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Patent Agency Ranking
公开(公告)号：US11757455B1
公开(公告)日：2023-09-12
申请号：US18046283
申请日：2022-10-13
Applicant: QUALCOMM Incorporated
Inventor： Sameer Wadhwa , Lennart Karl-Axel Mathe
CPC classification number: H03L7/0818 , H03K5/13 , H03K2005/00019
Abstract: A delay cell for a delay locked loop, DLL, based serial link is disclosed. The delay cell has a first stage and a second stage, wherein an output of the first stage is an input to the second stage, the first stage comprising a resistive digital to analog converter, R-DAC and the second stage comprising a current starved delay cell.
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公开(公告)号：US20170085176A1
公开(公告)日：2017-03-23
申请号：US14857080
申请日：2015-09-17
Applicant: QUALCOMM Incorporated
Inventor： Lennart Karl-Axel Mathe
IPC: H02M3/158
CPC classification number: H02M3/158 , H02M3/1584
Abstract: In one embodiment, a switching regulator includes a first switching regulator stage configured between an input voltage and a first reference voltage and a second switching regulator stage configured between the first reference voltage and a second reference voltage. A first terminal of an inductor is coupled to an output of the first switching regulator stage and an output of the second switching regulator stage. The first switching regulator stage operates to produce an output voltage when the output voltage is configured above the first reference voltage, and the second switching regulator stage operates to produce an output voltage when the output voltage is configured below the first reference voltage.
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公开(公告)号：US09537450B2
公开(公告)日：2017-01-03
申请号：US14488114
申请日：2014-09-16
Applicant: QUALCOMM Incorporated
Inventor： Lennart Karl-Axel Mathe , Pengfei Li , Song S. Shi , Yunfei Shi , Joseph D. Rutkowski
CPC classification number: H03F1/0222 , H03F1/0227 , H03F3/19 , H03F3/21 , H03F3/245 , H03F2200/102 , H03F2200/451
Abstract: Techniques for dynamically generating a headroom voltage for an envelope tracking system. In an aspect, an initial headroom voltage is updated when a signal from a power amplifier (PA) indicates that the PA headroom is insufficient. The initial headroom voltage may be updated to an operating headroom voltage that includes the initial voltage plus a deficiency voltage plus a margin. In this manner, the operating headroom voltage may be dynamically selected to minimize power consumption while still ensuring that the PA is linear. In a further aspect, a specific exemplary embodiment of a headroom voltage generator using a counter is described.
Abstract translation: 用于动态产生包络跟踪系统的净空电压的技术。 在一方面，当来自功率放大器（PA）的信号指示PA余量不足时，更新初始余量电压。 初始余量电压可以被更新为包括初始电压加上缺陷电压加上余量的操作净空电压。 以这种方式，可以动态选择操作净空电压以最小化功耗，同时仍然确保PA是线性的。 在另一方面，描述了使用计数器的净空电压发生器的具体示例性实施例。
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9.发明授权公开(公告)号：US09379668B1
公开(公告)日：2016-06-28
申请号：US14675424
申请日：2015-03-31
Applicant: QUALCOMM Incorporated
Inventor： Jongrit Lerdworatawee , Song Shi , Lennart Karl-Axel Mathe
CPC classification number: H03F1/0216 , H03F1/0222 , H03F3/211 , H03F2200/102 , H03F2200/453 , H03F2200/78
Abstract: The present disclosure includes envelope tracking circuits and methods with adaptive switching frequency. In one embodiment, a circuit comprising an amplifier to receive an envelope tracking signal having an envelope tracking frequency and output voltage and current to a power supply terminal of a power amplifier circuit. A programmable comparator receives an output signal from the amplifier and generates a switching signal having a switching frequency. A switching regulator stage receives the switching signal and outputs a switching current to the power supply terminal. A frequency comparison circuit configures the programmable comparator based on the envelope tracking frequency and the switching frequency so that the switching frequency tracks the envelope tracking frequency.
Abstract translation: 本公开包括具有自适应切换频率的包络跟踪电路和方法。 在一个实施例中，一种包括放大器的电路，用于接收具有包络跟踪频率的包络跟踪信号，并将输出电压和电流输出到功率放大器电路的电源端。 可编程比较器从放大器接收输出信号并产生具有开关频率的开关信号。 开关稳压器级接收开关信号并向开关端输出开关电流。 频率比较电路根据包络跟踪频率和开关频率配置可编程比较器，使得开关频率跟踪包络跟踪频率。
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公开(公告)号：US09124231B2
公开(公告)日：2015-09-01
申请号：US13752282
申请日：2013-01-28
Applicant: QUALCOMM Incorporated
Inventor： Song S Shi , Pengfei Li , Lennart Karl-Axel Mathe
CPC classification number: H03G1/0005 , H02M1/088 , H02M3/158 , H02M2001/0045 , H02M2001/0058 , Y02B70/1491
Abstract: Techniques for reducing ringing arising from L-C coupling in a boost converter circuit during a transition from a boost ON state to a boost OFF state. In an aspect, during an OFF state of the boost converter circuit, the size of the high-side switch coupling a boost inductor to the load is gradually increased over time. In this manner, the on-resistance of the high-side switch is decreased from a first value to a second (lower) value over time, which advantageously reduces ringing (due to high quality factor or Q) when initially entering the OFF state, while maintaining low conduction losses during the remainder of the OFF state. Further techniques are provided for implementing the high-side switch as a plurality of parallel-coupled transistors.
Abstract translation: 在升压转换电路从升压导通状态转换到升压关断状态时，减少由升压转换器电路中的L-C耦合引起振铃的技术。 在一方面，在升压转换器电路的OFF状态期间，将升压电感器耦合到负载的高侧开关的尺寸随时间逐渐增加。 以这种方式，高边开关的导通电阻随着时间从第一值降低到第二（较低）值，这有利于当初始进入截止状态时减少振铃（由于高品质因数或Q） 同时在关闭状态的剩余期间保持低导通损耗。 提供了用于将高侧开关实现为多个并联耦合晶体管的进一步技术。
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