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    Segmented successive approximation register (SAR) analog-to-digital converter (ADC) with reduced conversion time
    2.
    发明授权
    Segmented successive approximation register (SAR) analog-to-digital converter (ADC) with reduced conversion time 有权

    公开(公告)号：US09608658B1

    公开(公告)日：2017-03-28

    申请号：US15014865

    申请日：2016-02-03

    Applicant: QUALCOMM Incorporated

    Inventor： Omid Rajaee ,  Liang Dai ,  Ganesh Kiran

    IPC: H03M1/12 ,  H03M1/38 ,  H03M1/10

    CPC classification number: H03M1/38 ,  H03M1/1009 ,  H03M1/1014 ,  H03M1/188

    Abstract: Certain aspects of the present disclosure provide a segmented successive approximation register (SAR) analog-to-digital converter (ADC). One example ADC generally includes a plurality of SAR ADC circuits each associated with a different voltage range segment of a voltage range for the ADC. Each SAR ADC circuit is configured to receive an analog signal input to the ADC and to output a digital signal based on the analog signal, the digital signal being representative of a voltage level of the analog signal when the voltage level of the analog signal is within the segment associated with the SAR ADC circuit. In certain aspects, the SAR ADC may include logic configured to control a digital output of the ADC based on one or more of the digital signals representative of the voltage level of the analog signal output by one or more of the plurality of SAR ADC circuits.

    CALIBRATED TEMPERATURE SENSING SYSTEM
    3.
    发明申请
    CALIBRATED TEMPERATURE SENSING SYSTEM 审中-公开
    校准温度传感系统

    公开(公告)号：US20160252409A1

    公开(公告)日：2016-09-01

    申请号：US14634371

    申请日：2015-02-27

    Applicant: QUALCOMM, Incorporated

    Inventor： Li Lu ,  Masoud Roham ,  Liang Dai ,  Anand Meruva

    IPC: G01K19/00 ,  G01K7/22

    CPC classification number: G01K19/00 ,  G01K7/01 ,  G01K7/22 ,  G01K15/005 ,  G05F3/225

    Abstract: Systems and methods for sensing temperature on a chip are described herein. In one aspect, a temperature sensing system includes a sensing circuit with matching diode devices for providing corresponding diode voltages proportional to currents through the diode devices. The system also includes a digital code calculation unit for generating a plurality of digital code values based on first and second reference voltages and the diode voltages and a digital calibration engine configured for computing a calibrated temperature based on the plurality of digital codes. The system further includes a switching circuit for routing the diode voltages, during first and second times, to diode voltage input terminals of the digital code calculation unit.

    Abstract translation: 本文描述了用于感测芯片上的温度的系统和方法。 在一个方面，温度感测系统包括具有匹配二极管器件的感测电路，用于提供与通过二极管器件的电流成比例的相应的二极管电压。 该系统还包括一个数字代码计算单元，用于基于第一和第二参考电压和二极管电压产生多个数字代码值，以及数字校准引擎，被配置为基于多个数字代码来计算校准温度。 该系统还包括用于在第一次和第二次期间将二极管电压布置到数字代码计算单元的二极管电压输入端的开关电路。

    Noise shaping for switching circuitry
    4.
    发明授权
    Noise shaping for switching circuitry 有权
    开关电路的噪声整形

    公开(公告)号：US09059793B2

    公开(公告)日：2015-06-16

    申请号：US13752159

    申请日：2013-01-28

    Applicant: QUALCOMM Incorporated

    Inventor： Song S Shi ,  Lennart Karl-Axel Mathe ,  Liang Dai

    IPC: G05F1/00 ,  H04B15/00 ,  G05F1/10 ,  H02M1/12 ,  H02M1/44 ,  H02M3/156 ,  H03F3/217 ,  H03F1/02

    CPC classification number: H04B15/00 ,  G05F1/10 ,  H02M1/12 ,  H02M1/44 ,  H02M3/156 ,  H03F1/0211 ,  H03F3/217 ,  H03F2200/432

    Abstract: Techniques for creating one or more notch frequencies in the power density spectrum of an output voltage generated by switching circuitry. In an aspect, high- and low-side switches are coupled to an output voltage via an inductor. The spectral power of the output voltage at one or more frequencies is estimated, and the estimated spectral power is provided to a switch controller controlling the switches. The switch controller may be configured to switch the switches only in response to detecting that the estimated spectral power at the notch frequency is at a minimum. In certain exemplary aspects, the techniques may be incorporated in an envelope-tracking system, wherein the switching circuitry forms part of a switched-mode power supply (SMPS) supplying low-frequency power to a power amplifier load.

    Abstract translation: 在由开关电路产生的输出电压的功率密度谱中产生一个或多个陷波频率的技术。 在一个方面，高侧和低侧开关通过电感耦合到输出电压。 估计在一个或多个频率处的输出电压的频谱功率，并且将估计的频谱功率提供给控制开关的开关控制器。 开关控制器可以被配置为仅响应于检测到陷波频率处的估计频谱功率为最小而切换开关。 在某些示例性方面，这些技术可以并入包络跟踪系统中，其中开关电路形成向功率放大器负载提供低频功率的开关模式电源（SMPS）的一部分。

    Low voltage, highly accurate current mirror
    5.
    发明授权
    Low voltage, highly accurate current mirror 有权

    公开(公告)号：US09898028B2

    公开(公告)日：2018-02-20

    申请号：US14755435

    申请日：2015-06-30

    Applicant: QUALCOMM Incorporated

    Inventor： Masoud Roham ,  Liang Dai

    IPC: G05F1/10 ,  G05F3/26 ,  G01R19/00 ,  H03F3/347 ,  H03F3/50

    CPC classification number: G05F3/262 ,  G01R19/0092 ,  H03F3/347 ,  H03F3/505 ,  H03F2200/453 ,  H03F2200/456 ,  H03F2200/474 ,  H03F2200/91

    Abstract: Certain aspects of the present disclosure generally relate to a low voltage, accurate current mirror, which may be used for distributed sensing of a remote current in an integrated circuit (IC). One example current mirror typically includes a first pair of transistors, a second pair of transistors in cascode with the first pair of transistors, a switching network coupled to the second pair of transistors, and a third pair of transistors coupled to the switching network. An input node between the first and second pairs of transistors may be configured to receive an input current for the current mirror, and an output node at the first pair of transistors may be configured to sink an output current for the current mirror, proportional to the input current. This current mirror architecture offers a hybrid low-voltage/high-voltage solution, tolerates low input voltages, provides high output impedance, and offers low area and power consumption.

    METAL CAPACITOR WITH INNER FIRST TERMINAL AND OUTER SECOND TERMINAL
    7.
    发明申请
    METAL CAPACITOR WITH INNER FIRST TERMINAL AND OUTER SECOND TERMINAL 审中-公开
    具有内部第一端子和外部第二端子的金属电容器

    公开(公告)号：US20140367827A1

    公开(公告)日：2014-12-18

    申请号：US13919790

    申请日：2013-06-17

    Applicant: QUALCOMM Incorporated

    Inventor： Bruce Sokki Lee ,  Liang Dai

    IPC: H01G4/228 ,  H01G13/00 ,  H01L29/94

    CPC classification number: H01G4/228 ,  H01G13/006 ,  H01L23/5223 ,  H01L23/5225 ,  H01L27/0733 ,  H01L27/0805 ,  H01L28/60 ,  H01L28/88 ,  H01L28/91 ,  H01L29/94 ,  H01L2924/0002 ,  Y10T29/43 ,  H01L2924/00

    Abstract: A metal capacitor with an inner first terminal (e.g., a positive terminal) and an outer second terminal (e.g., a negative terminal) is disclosed herein. In an exemplary design, an apparatus (e.g., an IC chip) includes a first conductive line for a first terminal of a capacitor and at least one conductive line for a second terminal of the capacitor. The at least one conductive line is formed on opposing first and second sides of the first conductive line. Parallel conductive traces are formed transverse to, and on both the first and second sides of, the first conductive line. Additional parallel conductive traces are formed transverse to the at least one conductive line and are interlaced with the parallel conductive traces coupled to the first conductive line. The metal capacitor includes a plurality of unit capacitors formed by the parallel conductive traces coupled to the conductive lines.

    Abstract translation: 本文公开了具有内部第一端子（例如，正极端子）和外部第二端子（例如，负极端子）的金属电容器。 在示例性设计中，装置（例如，IC芯片）包括用于电容器的第一端子的第一导线和用于电容器的第二端子的至少一个导线。 所述至少一条导线形成在所述第一导线的相对的第一和第二侧上。 平行导电迹线横向于第一导线的第一和第二侧上并且在第一和第二侧上形成。 附加的平行导电迹线横向于至少一条导电线形成并且与耦合到第一导线的平行导电迹线交错。 金属电容器包括由耦合到导线的平行导电迹线形成的多个单位电容器。

    Analog-to-digital converter, phase sampler, time-to-digital converter, and flip-flop
    8.
    发明授权
    Analog-to-digital converter, phase sampler, time-to-digital converter, and flip-flop 有权

    公开(公告)号：US11569801B2

    公开(公告)日：2023-01-31

    申请号：US17198515

    申请日：2021-03-11

    Applicant: QUALCOMM INCORPORATED

    Inventor： Liang Dai ,  Kentaro Yamamoto ,  Behnam Sedighi

    IPC: H03M1/00 ,  H03K3/356 ,  H03M3/00

    Abstract: A D-type flip-flop (DFF) includes an input circuit having a plurality of transistors configured to receive a clock signal and a data signal, a first inverter (INV1) having a pair of transistors, the first inverter configured to receive an input voltage (x) from the input circuit at a first inverter input, the first inverter configured to provide an output voltage (y) to a first inverter output, a second inverter (INV2) coupled to the first inverter (INV1), the second inverter having a second inverter input and a second inverter output, the second inverter input coupled to the first inverter output, a third inverter (INV3) coupled to the second inverter (INV2), the third inverter having a third inverter input and a third inverter output, and a current device coupled to the first inverter output, the current device configured to provide a current at the first inverter output.

    NOISE SHAPING FOR SWITCHING CIRCUITRY
    10.
    发明申请
    NOISE SHAPING FOR SWITCHING CIRCUITRY 有权
    噪声形成开关电路

    公开(公告)号：US20140213208A1

    公开(公告)日：2014-07-31

    申请号：US13752159

    申请日：2013-01-28

    Applicant: QUALCOMM INCORPORATED

    Inventor： Song S. Shi ,  Lennart Karl-Axel Mathe ,  Liang Dai

    IPC: H04B15/00 ,  G05F1/10

    CPC classification number: H04B15/00 ,  G05F1/10 ,  H02M1/12 ,  H02M1/44 ,  H02M3/156 ,  H03F1/0211 ,  H03F3/217 ,  H03F2200/432

    Abstract: Techniques for creating one or more notch frequencies in the power density spectrum of an output voltage generated by switching circuitry. In an aspect, high- and low-side switches are coupled to an output voltage via an inductor. The spectral power of the output voltage at one or more frequencies is estimated, and the estimated spectral power is provided to a switch controller controlling the switches. The switch controller may be configured to switch the switches only in response to detecting that the estimated spectral power at the notch frequency is at a minimum. In certain exemplary aspects, the techniques may be incorporated in an envelope-tracking system, wherein the switching circuitry forms part of a switched-mode power supply (SMPS) supplying low-frequency power to a power amplifier load.

    Abstract translation: 在由开关电路产生的输出电压的功率密度谱中产生一个或多个陷波频率的技术。 在一个方面，高侧和低侧开关通过电感耦合到输出电压。 估计在一个或多个频率处的输出电压的频谱功率，并且将估计的频谱功率提供给控制开关的开关控制器。 开关控制器可以被配置为仅响应于检测到陷波频率处的估计频谱功率为最小而切换开关。 在某些示例性方面，这些技术可以并入包络跟踪系统中，其中开关电路形成向功率放大器负载提供低频功率的开关模式电源（SMPS）的一部分。

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