公开(公告)号：US12206001B2

公开(公告)日：2025-01-21

申请号：US16526756

申请日：2019-07-30

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Haining Yang ,  Xia Li

IPC: H01L29/423 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088

Abstract: A semiconductor device is disclosed that includes a plurality of fins on a substrate. A long channel gate is disposed over a first portion of the plurality of fins. A gate contact is provided having an extended portion that extends into an active area from a gate contact base outside the active area.

公开(公告)号：US20240096964A1

公开(公告)日：2024-03-21

申请号：US17933568

申请日：2022-09-20

Applicant: QUALCOMM Incorporated

Inventor： Junjing Bao ,  Xia Li ,  Giridhar Nallapati

IPC: H01L29/10 ,  H01L27/092 ,  H01L29/08 ,  H01L29/165 ,  H01L29/40 ,  H01L29/417 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/1037 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/401 ,  H01L29/41741 ,  H01L29/4991 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7848

Abstract: Vertical channel field-effect transistors (VCFETs) with reduced contact resistance and/or parasitic capacitance, and related fabrication methods. In exemplary aspects, to reduce contact resistance of the VCFET, an end portion of the vertical channel has a semiconductor structure that has an expanded width in the horizontal direction parallel to the substrate surface. This provides a greater area to form a contact for a source/drain to reduce contact resistance of the VCFET. To reduce the parasitic capacitance between the gate and a contact of the VCFET, the spacer includes one or more air gaps that form an air spacer(s) between the gate and the contact to reduce the overall average permittivity of the spacer. In one example, the air spacer(s) of the VCFET is elongated in the horizontal direction parallel to the substrate surface (and perpendicular to the vertical direction of the vertical channel) to further reduce the parasitic capacitance.

公开(公告)号：US11545483B2

公开(公告)日：2023-01-03

申请号：US16712222

申请日：2019-12-12

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Haining Yang ,  Bin Yang

IPC: H01L27/06 ,  H01L29/04 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/762 ,  H01L29/78

Abstract: Certain aspects of the present disclosure are directed to a semiconductor device. The semiconductor device generally includes a substrate, at least one silicon-on-insulator (SOI) transistor disposed above the substrate, a gate-all-around (GAA) transistor disposed above the substrate, and a fin field-effect transistor (FinFET) disposed above the substrate.

公开(公告)号：US11515406B2

公开(公告)日：2022-11-29

申请号：US16379904

申请日：2019-04-10

Applicant: QUALCOMM Incorporated

Inventor： Gengming Tao ,  Bin Yang ,  Xia Li

IPC: H01L29/737 ,  H01L29/40 ,  H01L29/66 ,  H03F3/19

Abstract: Aspects generally relate to a heterojunction bipolar transistor (HBT), and method of manufacturing the same. The HBT including an emitter a first, a first side of a base coupled to a second side of the emitter opposite the first side of the emitter. A collector coupled to the base on a second side of the base opposite the emitter, wherein an area of a junction between the base and the collector is less than or equal to an area of a junction between the base and the emitter. A dielectric coupled to the collector. A first conductive base contact coupled to the base and adjacent to the collector and extending over a base-collector junction, the conductive base contact operative as a field plate.

公开(公告)号：US11494629B2

公开(公告)日：2022-11-08

申请号：US16669855

申请日：2019-10-31

Applicant: QUALCOMM Incorporated

Inventor： Zhongze Wang ,  Xia Li ,  Xiaochun Zhu

IPC: G11C16/08 ,  G06N3/063 ,  G11C11/419 ,  G11C11/412 ,  G11C11/21

Abstract: Certain aspects provide a circuit for in-memory computation. The circuit generally includes a first memory cell, and a first computation circuit. The first computation circuit may include a first switch having a control input coupled to an output of the first memory cell, a second switch coupled between a node of the first computation circuit and the first switch, a control input of the second switch being coupled to a discharge word-line (DCWL), a capacitive element coupled between the node and a reference potential node, a third switch coupled between the node and a read bit-line (RBL), and a fourth switch coupled between the node and an activation (ACT) line.

公开(公告)号：US10964380B1

公开(公告)日：2021-03-30

申请号：US16784149

申请日：2020-02-06

Applicant: QUALCOMM Incorporated

Inventor： Zhongze Wang ,  Yandong Gao ,  Xia Li ,  Ye Lu ,  Xiaochun Zhu ,  Xiaonan Chen

IPC: G11C11/41 ,  G11C11/412 ,  G11C11/56 ,  G11C11/419 ,  H01L27/11 ,  G11C11/418 ,  H01L23/528 ,  H01L23/522 ,  H01L23/00

Abstract: A memory circuit that includes a memory bitcell. The memory bitcell includes a six-transistor circuit configuration, a first transistor coupled to the six-transistor circuit configuration, a second transistor coupled to the first transistor, a third transistor coupled to the second transistor, and a capacitor coupled to the second transistor and the third transistor. The memory circuit includes a read word line coupled to the third transistor, a read bit line coupled to the third transistor, and an activation line coupled to the second transistor. The memory bitcell may be configured to operate as a NAND memory bitcell. The memory bitcell may be configured to operate as a NOR memory bitcell.

公开(公告)号：US10923436B2

公开(公告)日：2021-02-16

申请号：US16362951

申请日：2019-03-25

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Kai Liu ,  Xia Li

IPC: H01L23/00 ,  H01L25/16 ,  H01L23/498 ,  H04W88/02 ,  H04W88/08

Abstract: Certain aspects of the present disclosure provide apparatus for thermal matching of integrated circuits (ICs). One example apparatus generally includes a first substrate, a first IC disposed on the first substrate and having a second substrate, and a second IC disposed on the first substrate. The second IC may include a third substrate, a thermal conductivity adjustment region comprising different material than the third substrate, the thermal conductivity adjustment region being adjacent to a first side of the third substrate, and one or more electrical components formed in one or more layers of the second IC adjacent to a second side of the third substrate, wherein the first side and the second side are opposite sides of the third substrate, and wherein a thermal conductivity of the thermal conductivity adjustment region is closer to a thermal conductivity of the second substrate than a thermal conductivity of the third substrate.

公开(公告)号：US10811068B2

公开(公告)日：2020-10-20

申请号：US16247247

申请日：2019-01-14

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Wei-Chuan Chen ,  Wah Nam Hsu ,  Seung Hyuk Kang

IPC: G11C11/16 ,  H01F10/32 ,  G11C11/15 ,  H01L43/08 ,  H01L27/22 ,  H01L43/12

Abstract: Varying energy barriers of magnetic tunnel junctions (MTJs) in different magneto-resistive random access memory (MRAM) arrays in a semiconductor die to facilitate use of MRAM for different memory applications is disclosed. In one aspect, energy barriers of MTJs in different MRAM arrays are varied. The energy barrier of an MTJ affects its write performance as the amount of switching current required to switch the magnetic orientation of a free layer of the MTJ is a function of its energy barrier. Thus, by varying the energy barriers of the MTJs in different MRAM arrays in a semiconductor die, different MRAM arrays may be used for different types of memory provided in the semiconductor die while still achieving distinct performance specifications. The energy barrier of an MTJ can be varied by varying the materials, heights, widths, and/or other characteristics of MTJ stacks.

公开(公告)号：US10734384B1

公开(公告)日：2020-08-04

申请号：US16255008

申请日：2019-01-23

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Bin Yang ,  Gengming Tao

IPC: H01L27/092 ,  H01L29/24 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L27/02 ,  H01L21/8238 ,  H01L29/08

Abstract: Vertically-integrated two-dimensional (2D) semiconductor slabs in Complementary Field-Effect Transistor (FET) (CFET) cell circuits are disclosed. A horizontal footprint of a CFET cell circuit may be reduced in an X-axis dimension by reducing a gate length of the N-type and P-type channel structures. The N-type and P-type channel structures may be formed of 2D semiconductor materials with high carrier mobility and strong on/off control, which allows a gate length of each semiconductor channel structure to be reduced without increasing a leakage current. By employing one or more elongated monolayers of 2D material in each slab, and vertically stacking slabs to form each semiconductor channel structure, a desired CFET drive strength may be adjusted according to a vertical dimension of the CFET cell circuit, while X-axis and Y-axis dimensions of the horizontal footprint are reduced.

公开(公告)号：US20200091448A1

公开(公告)日：2020-03-19

申请号：US16130457

申请日：2018-09-13

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Bin Yang ,  Gengming Tao

IPC: H01L51/05 ,  H01L51/00 ,  H01L27/06

Abstract: Three-dimensional (3D) carbon nanotube gate field-effect transistors (FETs), that use carbon nanotubes to form a gate, and related fabrication methods are disclosed. A carbon nanotube gate can provide for greater channel control and enlarge the effective channel width of the 3D FET, thus increasing drive strength. Carbon nanotubes have lower surface scatter and have been found to be diffusive such that resistance dominates carrier transport, thus causing higher carrier mobility. A 3D FET can be provided that includes a gate formed from carbon nanotube(s) disposed adjacent to a semiconductor channel formed from a carbon nanotube(s). A dual-gate FET can be provided employing a carbon nanotube gate(s) comprising a front and back carbon nanotube with a semiconductor channel formed therebetween.