公开(公告)号：US20240055356A1

公开(公告)日：2024-02-15

申请号：US18492402

申请日：2023-10-23

Applicant: QUALCOMM Incorporated

Inventor： Bharani CHAVA ,  Abinash ROY ,  Stanley Seungchul SONG ,  Jonghae KIM

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00

CPC classification number: H01L23/5385 ,  H01L24/16 ,  H01L24/81 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16227

Abstract: A package comprising a substrate; a first integrated device coupled to the substrate through at least a first plurality of solder interconnects; a second integrated device coupled to the substrate through at least a second plurality of solder interconnects; a first bridge coupled to the first integrated device and the second integrated device through at least a third plurality of solder interconnects, wherein the first bridge is configured to provide at least one first electrical path between the first integrated device and the second integrated device, and wherein the first bridge is coupled to a top portion of the first integrated device and a top portion of the second integrated device, through at least the third plurality of solder interconnects; and a second bridge coupled to the first integrated device and the second integrated device through a fourth plurality of solder interconnects.

公开(公告)号：US20220415808A1

公开(公告)日：2022-12-29

申请号：US17357811

申请日：2021-06-24

Applicant: QUALCOMM Incorporated

Inventor： Bharani CHAVA ,  Abinash ROY ,  Stanley Seungchul SONG ,  Jonghae KIM

IPC: H01L23/538 ,  H01L25/10 ,  H01L25/00 ,  H01L23/00

Abstract: A package comprising a substrate, a first integrated device coupled to the substrate, a second integrated device coupled to the substrate, a first bridge and a second bridge. The first bridge is coupled to the first integrated device and the second integrated device. The first bridge is configured to provide at least one first electrical path between the first integrated device and the second integrated device. The first bridge is coupled to a top portion of the first integrated device and a top portion of the second integrated device. The second bridge is coupled to the first integrated device and the second integrated device. The second bridge is configured to provide at least one second electrical path between the first integrated device and the second integrated device.

公开(公告)号：US20200264682A1

公开(公告)日：2020-08-20

申请号：US16276532

申请日：2019-02-14

Applicant: QUALCOMM Incorporated

Inventor： Dipti Ranjan PAL ,  Jeffrey GEMAR ,  Abinash ROY

IPC: G06F1/324 ,  G06F1/3237 ,  G06F1/08

Abstract: In certain aspects, an apparatus includes a first power chain, a second power chain, and an enable circuit having an output coupled to an input of the first power chain. The apparatus also includes a multiplexer having a first input coupled to an output of the first power chain, a second input coupled to the output of the enable circuit, and an output coupled to an input of the second power chain, wherein the multiplexer is configured to receive a select signal, and couple the first input or the second input to the output of the multiplexer based on the select signal.

公开(公告)号：US20230387077A1

公开(公告)日：2023-11-30

申请号：US18365063

申请日：2023-08-03

Applicant: QUALCOMM Incorporated

Inventor： Bharani CHAVA ,  Abinash ROY

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/498 ,  H01L23/58 ,  H01L23/00 ,  H03K17/687

CPC classification number: H01L25/0655 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/58 ,  H01L24/16 ,  H03K17/6871 ,  H01L2224/16227

Abstract: A package that includes a substrate and integrated device coupled to the substrate. The integrated device includes a first core and a second core. The substrate includes a first power interconnect configured to provide a first electrical path for a first power resource to the first core of the integrated device. The first power interconnect includes a first power plane. The substrate includes a second power interconnect configured to provide a second electrical path for a second power resource to the second core of the integrated device. The second power interconnect includes a second power plane. The substrate includes a switch coupled to the first power interconnect and the second power interconnect, where if the switch is turned on, the switch is configured to enable at least some of the power resource from the second power resource to contribute to the first core of the integrated device.

公开(公告)号：US20220246580A1

公开(公告)日：2022-08-04

申请号：US17162621

申请日：2021-01-29

Applicant: QUALCOMM Incorporated

Inventor： Bharani CHAVA ,  Abinash ROY

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/58 ,  H01L23/00 ,  H01L23/31 ,  H03K17/687

Abstract: A package that includes a substrate and integrated device coupled to the substrate. The integrated device includes a first core and a second core. The substrate includes a first power interconnect configured to provide a first electrical path for a first power resource to the first core of the integrated device. The substrate includes a second power interconnect configured to provide a second electrical path for a second power resource to the second core of the integrated device. The substrate includes a switch coupled to the first power interconnect and the second power interconnect, where if the switch is turned on, the switch is configured to enable at least some of the power resource from the second power resource to contribute to the first core of the integrated device.

公开(公告)号：US20210408015A1

公开(公告)日：2021-12-30

申请号：US16917212

申请日：2020-06-30

Applicant: QUALCOMM Incorporated

Inventor： Abinash ROY ,  Bharani CHAVA

IPC: H01L27/112 ,  H01L23/538 ,  H01L21/48

Abstract: Disclosed are devices and methods having a programmable resistor and an on-package decoupling capacitor (OPD). In one aspect a package includes an OPD and a programmable resistor formed from at least one thin-film transistor (TFT). The programmable resistor is disposed in series with the OPD between a supply voltage (VDD) conductor and a ground conductor.

公开(公告)号：US20220415868A1

公开(公告)日：2022-12-29

申请号：US17358838

申请日：2021-06-25

Applicant: QUALCOMM Incorporated

Inventor： Abinash ROY ,  Lohith Kumar VEMULA ,  Bharani CHAVA ,  Jonghae KIM

IPC: H01L25/16 ,  H01L23/13 ,  H01L21/48 ,  H01L23/498 ,  H01L23/64

Abstract: A package comprising a substrate and an integrated device coupled to the substrate. The substrate includes at least one dielectric layer, a plurality of interconnects comprising a first interconnect and a second interconnect, a capacitor located at least partially in the substrate, the capacitor comprising a first terminal and a second terminal, a first solder interconnect coupled to a first side surface of the first terminal and the first interconnect, and a second solder interconnect coupled to a second side surface of the second terminal and the second interconnect.

公开(公告)号：US20220077109A1

公开(公告)日：2022-03-10

申请号：US17015308

申请日：2020-09-09

Applicant: QUALCOMM Incorporated

Inventor： Bharani CHAVA ,  Stanley Seungchul SONG ,  Abinash ROY ,  Jonghae KIM

IPC: H01L25/065 ,  H01L23/00 ,  H01L21/78 ,  H01L25/00

Abstract: An integrated circuit (IC) package is described. The IC package includes a first die having a first power delivery network on the first die. The IC package also includes a second die having a second power delivery network on the second die. The first die is stacked on the second die. The IC package further includes package voltage regulators integrated with and coupled to the first die and/or the second die within a package core of the integrated circuit package.

公开(公告)号：US20200019229A1

公开(公告)日：2020-01-16

申请号：US16033014

申请日：2018-07-11

Applicant: QUALCOMM Incorporated

Inventor： Raghavendra SRINIVAS ,  Abhijit JOSHI ,  Bharat KAVALA ,  Abinash ROY

IPC: G06F1/32 ,  G06F1/28

Abstract: Systems and methods for power sequencing include, for an integrated circuit comprising one or more logic instances, one or more power multiplexers to select from at least a first power rail and a second power rail, an active power rail to supply power to the one or more logic instances. One or more sequence multiplexers are used to choose from at least a first power sequence for the first power rail and a second power sequence for the second power rail, an active power sequence. One or more head switches coupled to the one or more logic instances are either turned on, in the active power sequence, to supply power to the one or more logic instances from the active power rail, or turned off, in the active power sequence, the one or more head switches, to power down the one or more logic instances.

公开(公告)号：US20190339757A1

公开(公告)日：2019-11-07

申请号：US15967872

申请日：2018-05-01

Applicant: QUALCOMM Incorporated

Inventor： Abinash ROY ,  Dipti Ranjan PAL ,  Avinash GADDE

IPC: G06F1/26

Abstract: Methods and apparatuses to power up multiple load circuits are presented. The apparatus includes a power delivery network, multiple load circuits configured to be powered via the power delivery network, and a wakeup control circuit configured to power up the multiple load circuits at a frequency based on a resonance frequency of the power delivery network. The method includes delivering power to the multiple load circuits by a power source via a power delivery network and powering up the multiple load circuits at a frequency, by a wakeup control circuit, based on a resonance frequency of the power delivery network.