公开(公告)号：US20250069965A1

公开(公告)日：2025-02-27

申请号：US18456295

申请日：2023-08-25

Applicant: QUALCOMM Incorporated

Inventor： Ryan LANE ,  Charles David PAYNTER ,  William STONE ,  Ahmer SYED ,  Yue LI ,  Kuiwon KANG ,  Wei WANG ,  Durodami LISK

IPC: H01L23/13 ,  H01L23/00

Abstract: A package comprising an integrated device and a substrate coupled to the integrated device through at least a plurality of solder interconnects. The substrate comprises at least one dielectric layer; a frame at least partially located in the at least one dielectric layer; and a plurality of interconnects located at least partially in the at least one dielectric layer. The frame may be an embedded frame.

公开(公告)号：US20240371806A1

公开(公告)日：2024-11-07

申请号：US18313020

申请日：2023-05-05

Applicant: QUALCOMM Incorporated

Inventor： Dongming HE ,  Jun CHEN ,  Yangyang SUN ,  Lily ZHAO ,  Ahmer SYED

IPC: H01L23/00 ,  H01L23/31

Abstract: Disclosed are techniques for integrated circuit device. In an aspect, an integrated circuit device includes a metallization structure that includes a top metal layer structure; a passivation layer on the metallization structure; a bump structure disposed on the first bump line structure; and a first polymer protection layer. The passivation layer may include one or more first openings. The first bump line structure may include one or more first extended portions respectively extending toward the top metal layer structure through the one or more first openings. The bump structure may be electrically coupled to the first bump line structure. The first polymer protection layer may be on the passivation layer, on a portion of the first bump line structure, and in contact with a side surface of the first bump line structure.

公开(公告)号：US20240079307A1

公开(公告)日：2024-03-07

申请号：US17939769

申请日：2022-09-07

Applicant: QUALCOMM Incorporated

Inventor： Wei WANG ,  Kuiwon KANG ,  Michelle Yejin KIM ,  Ahmer SYED

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2924/35121

Abstract: A package comprising an integrated device and a substrate coupled to the integrated device. The substrate comprises at least one dielectric layer and a plurality of interconnects. The plurality of interconnects include a plurality of post interconnects. The plurality of post interconnects include a post interconnect comprising a profile cross section that includes a trapezoid shape.