公开(公告)号：US20240273051A1

公开(公告)日：2024-08-15

申请号：US18169764

申请日：2023-02-15

Applicant: QUALCOMM Incorporated

Inventor： Ziv LANDESBERG ,  Gil ZUKER ,  Tom YAHALOM ,  Ziv HOROVITZ ,  Adi MENACHEM ,  Tomer Rafael BEN-CHEN ,  Amit GIL

IPC: G06F13/42 ,  G06F13/38

CPC classification number: G06F13/4282 ,  G06F13/382 ,  G06F2213/0042

Abstract: Some aspects of the disclosure provide various techniques for tunneling a Universal Serial Bus (USB) packet using cut-through techniques in a USB4 system. The disclosed cut-through techniques can avoid the use of store-and-forward (SAF) operations to tunnel a USB3 packet (e.g., USB 3.2 packet) through a USB4 link so that the latency of the tunneled USB3 packet can be reduced. Furthermore, the disclosed cut-through techniques can reduce the need for a large data buffer in a USB controller/adapter when SAF operations are used to tunnel USB3 packets.

公开(公告)号：US20190236042A1

公开(公告)日：2019-08-01

申请号：US16219698

申请日：2018-12-13

Applicant: QUALCOMM Incorporated

Inventor： Helena Deirdre O'SHEA ,  Lalan Jee MISHRA ,  Amit GIL ,  Gary CHANG ,  Mohit Kishore Prasad ,  Richard Dominic WIETFELDT ,  Vinay JAIN

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/404 ,  G06F13/4022 ,  G06F13/4031 ,  G06F13/4291 ,  G06F2213/0052 ,  G06F2213/36

Abstract: In a device comprising a serial bus and a plurality of devices, register/address mappings and/or unique group identifiers are used to convey additional information in messages/datagrams over the serial bus without explicitly sending such information in the message/datagram. Such register/address mappings may be done beforehand, and in conjunction with group-specific identifiers, may reduce transmission latency by keeping the size of the messages/datagrams small. Since all devices on the serial bus have prior knowledge of such register/address mappings and/or group-specific identifiers, recipient devices are able to infer information from the group-specific identifiers and/or register/address sent in each message/datagram that is not explicitly sent within such message/datagram.

公开(公告)号：US20190107882A1

公开(公告)日：2019-04-11

申请号：US16155824

申请日：2018-10-09

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee MISHRA ,  James Lionel PANIAN ,  Richard Dominic WIETFELDT ,  Mohit Kishore PRASAD ,  Amit GIL ,  Shaul Yohai YIFRACH

IPC: G06F1/32 ,  G06F13/10 ,  G06F13/40

Abstract: A system for low-speed Peripheral Component Interconnect (PCI) Express (PCIe) systems, while maintaining both lower level physical layer (PHY) pin requirements and upper layer functionality being capable of both differential and single-ended signaling modes optimized for power savings. An apparatus includes an integrated circuit (IC) adapted to be connected to a Peripheral Component Interconnect (PCI) Express (PCIe) bus. The IC includes a control block selects between differential and single-ended signaling for the PCIe bus. The single-ended signaling is transmitted through existing pins of the IC that are coupled to the PCIe bus for differential signaling when single-ended signaling is selected for the PCIe bus.

公开(公告)号：US20190095273A1

公开(公告)日：2019-03-28

申请号：US16123737

申请日：2018-09-06

Applicant: QUALCOMM Incorporated

Inventor： Sharon GRAIF ,  Amit GIL ,  David TEB ,  Radu PITIGOI-ARON

IPC: G06F11/10 ,  G06F1/04 ,  G06F11/07 ,  G06F13/42

Abstract: Systems, methods, and apparatus are described that enable a serial bus to be operated in one or more modes that employ additional wires for communicating data. An apparatus has a bus including a first lane and a second lane, a plurality of devices coupled to the bus and, in a first mode of operation, the plurality of devices is configured to exchange data in a signal transmitted on the first lane in accordance with timing provided by a clock signal transmitted on the second lane. The apparatus may include one or more additional lanes connecting two or more devices in the plurality of devices, the two or more devices being configured to use the first lane and at least one of the additional lanes for data transmissions in a second mode of operation.

公开(公告)号：US20190227962A1

公开(公告)日：2019-07-25

申请号：US16193853

申请日：2018-11-16

Applicant: QUALCOMM Incorporated

Inventor： Helena Deirdre O'SHEA ,  Lalan Jee MISHRA ,  Richard Dominic WIETFELDT ,  Mohit Kishore PRASAD ,  Amit GIL ,  Gary CHANG

IPC: G06F13/20 ,  G06F13/42

CPC classification number: G06F13/20 ,  G06F13/4282

Abstract: Systems, methods, and apparatus are described that provide for communicating coexistence messages over a multi-drop serial bus. A data communication method includes configuring a common memory map at each of a plurality of devices coupled to a serial bus, receiving at a first device coupled to the serial bus, first coexistence information directed to a second device coupled to the serial bus, generating at the first device, a coexistence message that includes the first coexistence information, and transmitting the coexistence message to the second device over the serial bus. The first coexistence information in the coexistence message may be addressed to a location in the common memory map calculated based on a destination address associated with the first coexistence information and a unique identifier of the first device.

公开(公告)号：US20180373659A1

公开(公告)日：2018-12-27

申请号：US16012532

申请日：2018-06-19

Applicant: QUALCOMM Incorporated

Inventor： Lior AMARILIO ,  Amit GIL ,  Sharon GRAIF

IPC: G06F13/364 ,  G06F1/08 ,  G06F3/16 ,  H04R3/00 ,  H04R3/12

Abstract: System, methods and apparatus are described that can improve available bandwidth on a SoundWire bus without increasing the number of pins used by the SoundWire bus. A method performed at a master device coupled to a SoundWire bus includes providing a clock signal by a first master device over a clock line of a SoundWire bus to a first slave device and a second slave device coupled to the SoundWire bus, transmitting first control information from the first master device to the first slave device over a first data line of the SoundWire bus, and transmitting second control information from the first master device to the second slave device over a second data line of the SoundWire bus. The first control information may be different from the second control information and is transmitted concurrently with the second control information.