公开(公告)号：US10044365B1

公开(公告)日：2018-08-07

申请号：US15843718

申请日：2017-12-15

Applicant: QUALCOMM Incorporated

Inventor： Liang Dai ,  Kentaro Yamamoto ,  Omid Rajaee ,  Li Lu ,  Dinesh Alladi ,  Changsok Han

IPC: H03M1/50 ,  H03L7/081 ,  H04W84/04 ,  H03M3/00

Abstract: Certain aspects of the present disclosure provide apparatus and techniques for analog-to-digital conversion using a time-to-digital converter (TDC). For example, certain aspects provide a quantizer using a TDC. The quantizer may include at least one first capacitive element and a set of switches configured to selectively couple a first terminal and a second terminal of the at least one first capacitive element to at least one input voltage source. The TDC may also include a reference voltage source, at least one switch coupled between the second terminal of the at least one first capacitive element and an output of the reference voltage source, a current source selectively coupled to the first terminal of the at least one first capacitive element, and a voltage sense circuit coupled to the first terminal of the at least one first capacitive element.

公开(公告)号：US09455737B1

公开(公告)日：2016-09-27

申请号：US15049933

申请日：2016-02-22

Applicant: QUALCOMM Incorporated

Inventor： Omid Rajaee ,  Changsok Han ,  Liang Dai ,  Seyed Arash Mirhaj ,  Ganesh Kiran

IPC: H03M3/00

CPC classification number: H03M3/464 ,  H03M1/1023 ,  H03M1/46 ,  H03M3/37 ,  H03M3/422 ,  H03M3/47

Abstract: Certain aspects of the present disclosure provide a delta-sigma modulator (DSM) using time-interleaved (TI) successive approximation register (SAR) analog-to-digital converters (ADCs). For example, two SAR ADCs may be configured to alternately sample and process an input signal and provide a feedback signal for the DSM using excess loop delay (ELD). In other aspects, the DSM may be implemented using a two-step SAR quantizer. For example, a first SAR ADC may sample an input signal to generate a most-significant bit (MSB) portion of an output of the DSM, while the second SAR ADC may subsequently sample a residue from the first SAR ADC conversion and generate a least-significant bit (LSB) portion of the output of the DSM. With these techniques, higher bandwidths may be obtained in high accuracy delta-sigma ADCs without using increased sampling rates.

Abstract translation: 本公开的某些方面提供了使用时间交织（TI）逐次逼近寄存器（SAR）模数转换器（ADC）的Δ-Σ调制器（DSM）。 例如，两个SAR ADC可以配置为交替采样和处理输入信号，并使用多余的环路延迟（ELD）为DSM提供反馈信号。 在其他方面，DSM可以使用两步SAR量化器来实现。 例如，第一SAR ADC可以采样输入信号以产生DSM的输出的最高有效位（MSB）部分，而第二SAR ADC可以随后从第一SAR ADC转换中采样残留，并产生最少 - DSM的输出的高位（LSB）部分。 利用这些技术，可以在高精度Δ-ΣADC中获得更高的带宽，而不使用提高的采样率。