公开(公告)号：US09246716B2

公开(公告)日：2016-01-26

申请号：US14663303

申请日：2015-03-19

Applicant: QUALCOMM Incorporated

Inventor： Dexter Tamio Chun ,  Sumeet Sethi ,  John Eaton ,  Vinodh Cuppu ,  Vikram Arora ,  Vaishnav Srinivas ,  Asim Muhammad Muneer ,  Isaac Berk

IPC: H03K19/003 ,  H04L25/02 ,  H03K19/0175 ,  G06F13/40 ,  H03K19/00

CPC classification number: H04L25/0278 ,  G06F13/4086 ,  H03K19/0005 ,  H03K19/017545 ,  Y02D10/14 ,  Y02D10/151

Abstract: A method of controlling signal termination includes providing first logic for selectively terminating signals received at a first device on a bidirectional data bus, providing second logic for selectively terminating signals received at a second device on the bidirectional data bus, sending first signals from the first device to the second device on the bidirectional data bus at a first speed, stopping the sending of the first signals, after stopping the sending of the first signals, enabling the second logic and shifting a reference voltage of the second device from a first level to a second level, after enabling the second logic at the second device, sending second signals from the first device to the second device on the bidirectional data bus at a higher speed, and controlling the first logic based on a speed of signals received at the first device on the bidirectional data bus.

公开(公告)号：US20230029696A1

公开(公告)日：2023-02-02

申请号：US17390274

申请日：2021-07-30

Applicant: QUALCOMM Incorporated

Inventor： Girish Bhat ,  Subbarao Palacharla ,  Jeffrey Shabel ,  Isaac Berk ,  Kedar Bhole ,  Vipul Gandhi ,  George Patsilaras ,  Sparsh Singhai

IPC: G06F12/084 ,  G06F1/3212

Abstract: Integrated circuits (ICs) employ subsystem shared cache memory for facilitating extension of low-power island (LPI) memory. An LPI subsystem and primary subsystems access a memory subsystem on a first access interface in a first power mode and the LPI subsystem accesses the memory subsystem by a second access interface in the low power mode. In the first power mode, the primary subsystems and the LPI subsystem may send a subsystem memory access request including a virtual memory address to a subsystem memory interface of the memory subsystem to access either data stored in an external memory or a version of the data stored in a shared memory circuit. In the low-power mode, the LPI subsystem sends an LPI memory access request including a direct memory address to an LPI memory interface of the memory subsystem to access the shared memory circuit to extend the LPI memory.

公开(公告)号：US09705620B2

公开(公告)日：2017-07-11

申请号：US14858437

申请日：2015-09-18

Applicant: QUALCOMM Incorporated

Inventor： Philip Michael Clovis ,  Michael Drop ,  Isaac Berk

IPC: H04J3/06 ,  H04L7/033 ,  G06F13/42 ,  G06F13/16

CPC classification number: H04J3/0658 ,  G06F13/1689 ,  G06F13/4291 ,  H04L7/0331

Abstract: A memory controller is provided to increment a source timestamp count responsive to a clock signal. Further, the memory controller associates the source timestamp count to a respective word for each endpoint in a plurality of endpoints. The memory controller transmits the received clock signal, a respective data word, and an associated source count to each endpoint. Each endpoint increments a destination count responsive to the clock signal. Each endpoint further transmits its respective word to an external memory responsive to the destination count being greater than or equal to the associated source count by a threshold margin.

公开(公告)号：US11803472B2

公开(公告)日：2023-10-31

申请号：US17390274

申请日：2021-07-30

Applicant: QUALCOMM Incorporated

Inventor： Girish Bhat ,  Subbarao Palacharla ,  Jeffrey Shabel ,  Isaac Berk ,  Kedar Bhole ,  Vipul Gandhi ,  George Patsilaras ,  Sparsh Singhai

IPC: G06F12/084 ,  G06F1/3212

CPC classification number: G06F12/084 ,  G06F1/3212 ,  G06F2212/62

Abstract: Integrated circuits (ICs) employ subsystem shared cache memory for facilitating extension of low-power island (LPI) memory. An LPI subsystem and primary subsystems access a memory subsystem on a first access interface in a first power mode and the LPI subsystem accesses the memory subsystem by a second access interface in the low power mode. In the first power mode, the primary subsystems and the LPI subsystem may send a subsystem memory access request including a virtual memory address to a subsystem memory interface of the memory subsystem to access either data stored in an external memory or a version of the data stored in a shared memory circuit. In the low-power mode, the LPI subsystem sends an LPI memory access request including a direct memory address to an LPI memory interface of the memory subsystem to access the shared memory circuit to extend the LPI memory.

公开(公告)号：US20170085331A1

公开(公告)日：2017-03-23

申请号：US14858437

申请日：2015-09-18

Applicant: QUALCOMM Incorporated

Inventor： Phillip Michael Clovis ,  Michael Drop ,  Isaac Berk

IPC: H04J3/06 ,  H04L7/033

CPC classification number: H04J3/0658 ,  G06F13/1689 ,  G06F13/4291 ,  H04L7/0331

Abstract: A memory controller is provided to increment a source timestamp count responsive to a clock signal. Further, the memory controller associates the source timestamp count to a respective word for each endpoint in a plurality of endpoints. The memory controller transmits the received clock signal, a respective data word, and an associated source count to each endpoint. Each endpoint increments a destination count responsive to the clock signal. Each endpoint further transmits its respective word to an external memory responsive to the destination count being greater than or equal to the associated source count by a threshold margin.