公开(公告)号：US12079055B2

公开(公告)日：2024-09-03

申请号：US17949968

申请日：2022-09-21

Applicant: QUALCOMM Incorporated

Inventor： James Lionel Panian ,  John Eaton ,  Lakshmi Baskaran ,  Shrinivas Gopalan Uppili

IPC: G06F1/28 ,  G06F13/42 ,  H03K19/0185

CPC classification number: G06F1/28 ,  G06F13/4221 ,  H03K19/018507 ,  G06F2213/0026

Abstract: Aspects relate to techniques for controlling signal voltage levels across a wired data link for data communication between apparatuses. A first device can advertise multiple supported signal voltage levels to a peer device connected by the wired data link. The devices can implement the same signal voltage level(s) or different signal voltage levels. The peer devices can compare and select a compatible signal voltage level for data communication. The first device can provide a signal voltage indication signal that is configurable to a plurality of voltage levels corresponding to a plurality of signal voltages. At least one of the plurality of voltage levels can indicate that the first device can operate the data link at a plurality of signal voltages. In some examples, the wired data link can be a peripheral component interconnect express (PCIe) link.

公开(公告)号：US09246716B2

公开(公告)日：2016-01-26

申请号：US14663303

申请日：2015-03-19

Applicant: QUALCOMM Incorporated

Inventor： Dexter Tamio Chun ,  Sumeet Sethi ,  John Eaton ,  Vinodh Cuppu ,  Vikram Arora ,  Vaishnav Srinivas ,  Asim Muhammad Muneer ,  Isaac Berk

IPC: H03K19/003 ,  H04L25/02 ,  H03K19/0175 ,  G06F13/40 ,  H03K19/00

CPC classification number: H04L25/0278 ,  G06F13/4086 ,  H03K19/0005 ,  H03K19/017545 ,  Y02D10/14 ,  Y02D10/151

Abstract: A method of controlling signal termination includes providing first logic for selectively terminating signals received at a first device on a bidirectional data bus, providing second logic for selectively terminating signals received at a second device on the bidirectional data bus, sending first signals from the first device to the second device on the bidirectional data bus at a first speed, stopping the sending of the first signals, after stopping the sending of the first signals, enabling the second logic and shifting a reference voltage of the second device from a first level to a second level, after enabling the second logic at the second device, sending second signals from the first device to the second device on the bidirectional data bus at a higher speed, and controlling the first logic based on a speed of signals received at the first device on the bidirectional data bus.

公开(公告)号：US20240206066A1

公开(公告)日：2024-06-20

申请号：US18069004

申请日：2022-12-20

Applicant: QUALCOMM Incorporated

Inventor： Christopher Kong Yee Chun ,  Mid Deng ,  John Eaton

IPC: H05K1/14 ,  H01R12/71 ,  H05K3/34 ,  H05K3/36

CPC classification number: H05K1/141 ,  H01R12/714 ,  H05K3/3442 ,  H05K3/368

Abstract: A hybrid circuit board device includes a hybrid circuit board with a second, child circuit board disposed into a recessed circuit board portion of a first, parent circuit board to combine functionality of the child circuit board and the parent circuit board without exceeding a maximum circuit board height. The parent circuit board includes a first circuit board portion having a first thickness in a thickness direction. First interconnects on the first circuit board portion can couple to a first IC component. The child circuit board includes second interconnects to couple a second IC component. The child circuit board is in the recessed circuit board portion and is coupled to the parent circuit board by at least one board interconnect. The recessed circuit board portion of the parent circuit board has a second thickness that is thinner, in the thickness direction, than the first thickness.

公开(公告)号：US11452246B2

公开(公告)日：2022-09-20

申请号：US17071408

申请日：2020-10-15

Applicant: QUALCOMM Incorporated

Inventor： Charles David Paynter ,  Ryan Lane ,  John Eaton ,  Amit Mano

IPC: H05K9/00 ,  H05K1/02 ,  H05K3/30 ,  H05K5/00 ,  H05K1/11

Abstract: A device that includes a board, a package and a patch substrate. The board includes a cavity. The package is coupled to a first side of the board. The package includes a substrate and an integrated device coupled to the substrate. The integrated device is located at least partially in the cavity of the board. The patch substrate is coupled to a second side of the board. The patch substrate is located over the cavity of the board. The patch substrate is configured as an electromagnetic interference (EMI) shield for the package.