公开(公告)号：US20190324512A1

公开(公告)日：2019-10-24

申请号：US16458940

申请日：2019-07-01

Applicant: QUALCOMM Incorporated

Inventor： Jason Edward PODAIMA ,  Christophe Denis Bernard AVOINNE ,  Manokanthan SOMASUNDARAM ,  Sina DENA ,  Paul Christopher John WIERCIENSKI ,  Bohuslav RYCHLIK ,  Steven John HALTER ,  Jaya Prakash SUBRAMANIAM GANASAN ,  Myil RAMKUMAR ,  Dipti Ranjan PAL

IPC: G06F1/26 ,  G06F1/3287 ,  G06F1/324 ,  G06F1/3234 ,  G06F1/10

Abstract: Methods and systems are disclosed for full-hardware management of power and clock domains related to a distributed virtual memory (DVM) network. An aspect includes transmitting, from a DVM initiator to a DVM network, a DVM operation, broadcasting, by the DVM network to a plurality of DVM targets, the DVM operation, and, based on the DVM operation being broadcasted to the plurality of DVM targets by the DVM network, performing one or more hardware optimizations comprising: turning on a clock domain coupled to the DVM network or a DVM target of the plurality of DVM targets that is a target of the DVM operation, increasing a frequency of the clock domain, turning on a power domain coupled to the DVM target based on the power domain being turned off, or terminating the DVM operation to the DVM target based on the DVM target being turned off.

公开(公告)号：US20170285705A1

公开(公告)日：2017-10-05

申请号：US15086054

申请日：2016-03-31

Applicant: QUALCOMM Incorporated

Inventor： Jason Edward PODAIMA ,  Christophe Denis Bernard AVOINNE ,  Manokanthan SOMASUNDARAM ,  Sina DENA ,  Paul Christopher John WIERCIENSKI ,  Bohuslav RYCHLIK ,  Steven John HALTER ,  Jaya Prakash SUBRAMANIAM GANASAN ,  Myil RAMKUMAR ,  Dipt Ranjan PAL

IPC: G06F1/26 ,  G06F1/10 ,  G06F12/08

CPC classification number: G06F1/266 ,  G06F1/10 ,  G06F1/324 ,  G06F1/3275 ,  G06F1/3287 ,  G06F12/08 ,  G06F2212/1028 ,  G06F2212/657 ,  G06F2212/683 ,  Y02D10/126 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/171

Abstract: Methods and systems are disclosed for full-hardware management of power and clock domains related to a distributed virtual memory (DVM) network. An aspect includes transmitting, from a DVM initiator to a DVM network, a DVM operation, broadcasting, by the DVM network to a plurality of DVM targets, the DVM operation, and, based on the DVM operation being broadcasted to the plurality of DVM targets by the DVM network, performing one or more hardware optimizations comprising: turning on a clock domain coupled to the DVM network or a DVM target of the plurality of DVM targets that is a target of the DVM operation, increasing a frequency of the clock domain, turning on a power domain coupled to the DVM target based on the power domain being turned off, or terminating the DVM operation to the DVM target based on the DVM target being turned off.

公开(公告)号：US20160350234A1

公开(公告)日：2016-12-01

申请号：US14859351

申请日：2015-09-20

Applicant: QUALCOMM Incorporated

Inventor： Jason Edward PODAIMA ,  Paul Christopher John WIERCIENSKI ,  Carlos Javier MOREIRA ,  Alexander MIRETSKY ,  Meghal VARIA ,  Kyle John ERNEWEIN ,  Manokanthan SOMASUNDARAM ,  Muhammad Umar CHOUDRY ,  Serag Monier GADELRAB

IPC: G06F12/10 ,  G06F12/08

CPC classification number: G06F12/1063 ,  G06F12/0806 ,  G06F12/0842 ,  G06F12/0844 ,  G06F12/0891 ,  G06F12/1009 ,  G06F12/1036 ,  G06F2212/1024 ,  G06F2212/50 ,  G06F2212/655 ,  G06F2212/682 ,  G06F2212/683 ,  G06F2212/684

Abstract: Systems and methods relate to performing address translations in a multithreaded memory management unit (MMU). Two or more address translation requests can be received by the multithreaded MMU and processed in parallel to retrieve address translations to addresses of a system memory. If the address translations are present in a translation cache of the multithreaded MMU, the address translations can be received from the translation cache and scheduled for access of the system memory using the translated addresses. If there is a miss in the translation cache, two or more address translation requests can be scheduled in two or more translation table walks in parallel.

Abstract translation: 系统和方法涉及在多线程存储器管理单元（MMU）中执行地址转换。 可以由多线程MMU接收两个或多个地址转换请求并并行处理以将地址转换检索到系统存储器的地址。 如果地址转换存在于多线程MMU的转换高速缓存中，则可以从转换高速缓存接收地址转换，并且使用转换的地址来调度系统存储器的访问。 如果翻译缓存中存在缺失，则两个或多个地址转换请求可以在两个或多个平移的平移表中进行调度。