公开(公告)号：US20170271175A1

公开(公告)日：2017-09-21

申请号：US15460062

申请日：2017-03-15

Applicant: QUALCOMM Incorporated

Inventor： Christopher James HEALY ,  John Patrick HOLMES ,  Michael James SOLIMANDO ,  Sun YUN ,  William Michael STONE ,  Rajendra PENDSE

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L21/563 ,  H01L21/565 ,  H01L23/295 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/14131 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/73204 ,  H01L2924/1816 ,  H01L2924/18161 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00015

Abstract: Disclosed is a die packaging structure comprising a semiconductor die, an encapsulant layer disposed around the semiconductor die, wherein a backside surface of the semiconductor die is exposed, and a conductive layer coupled to the semiconductor die, the conductive layer comprising a plurality of conductive pillar bumps, wherein a bump density of the plurality of conductive pillar bumps is greater than 5%, wherein the encapsulant layer is further disposed between the plurality of conductive bumps, and wherein the encapsulant layer is disposed between the plurality of conductive bumps using a mold underfill (MUF) process. A method of forming the same is also disclosed.

公开(公告)号：US20210375845A1

公开(公告)日：2021-12-02

申请号：US16885171

申请日：2020-05-27

Applicant: QUALCOMM Incorporated

Inventor： William Michael STONE ,  Ryan LANE ,  Ahmer Raza SYED

IPC: H01L25/18 ,  H01L23/498 ,  H01L23/00 ,  H01L21/56

Abstract: An integrated circuit (IC) package is described. The IC package includes a package die and die interconnects on an active surface of the package die. The IC package also includes an integrated passive device (IPD) coupled to the active surface of the package die, between the plurality of die interconnects. A portion of the IPD extends beyond a Z-height of the die interconnects. The IC package further includes a package substrate coupled to the die interconnects, the package substrate having a cavity to receive the portion of the IPD.

公开(公告)号：US20190287929A1

公开(公告)日：2019-09-19

申请号：US16428441

申请日：2019-05-31

Applicant: QUALCOMM Incorporated

Inventor： William Michael STONE

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L23/528 ,  H01L21/768 ,  H01L23/522

Abstract: An integrated circuit (IC) device that includes an IC device layer, at least one electrical connection layer located over the IC device layer, and a varying diameter via layer located over the at least one electrical connection layer. The varying diameter via layer includes (i) an interior region having a plurality of interior region vias and (ii) a perimeter region having a plurality of perimeter region vias. The plurality of interior region vias of the interior region is larger than the plurality of perimeter region vias of the perimeter region. The varying diameter via layer comprises an interior surface that is coupled to an interior surface of the at least one electrical connection layer.

公开(公告)号：US20180151513A1

公开(公告)日：2018-05-31

申请号：US15800837

申请日：2017-11-01

Applicant: QUALCOMM Incorporated

Inventor： William Michael STONE

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L23/562 ,  H01L21/563 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/3171 ,  H01L23/5226 ,  H01L23/5283 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/13025 ,  H01L2224/13101 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/35121 ,  H01L2924/014 ,  H01L2924/00014

Abstract: An integrated circuit (IC) device includes a device layer and a passivation layer, where the passivation layer has vias formed in an interior region of the passivation layer that are larger than vias formed in a perimeter region of the passivation layer. As such, a varying diameter via layer is provided. The interior region vias may be configured to reduce a risk of damage to the IC device due to tensile stress, with sizes or shapes selected based on the amount of tensile stress expected to occur during subsequent use of the IC device. The perimeter region vias may be configured to reduce a risk of damage to the IC device due to sheer stress, with sizes or shapes selected based on the amount of sheer stress expected to occur during subsequent assembly or use of the IC device. Method and apparatus examples are described for use with flip-chip dies.