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公开(公告)号：US20160322689A1
公开(公告)日：2016-11-03
申请号：US14702044
申请日：2015-05-01
IPC分类号： H01P3/06
CPC分类号： H01P3/06 , H03K3/38 , H03K19/195
摘要： A microwave circuit is provided that comprises a plurality of transmission lines each configured to receive and propagate a respective waveform signal of a plurality of waveform signals, and a combiner that receives and combines the plurality of waveform signals from outputs of the plurality of transmission lines into a combined output waveform signal that is output terminated by an output termination resistor. The microwave circuit further comprises a compensation signal generator that generates a compensation signal to mitigate reflections associated with the transmission of signals through the microwave circuit.
摘要翻译： 提供一种微波电路，其包括多个传输线，每个传输线被配置为接收和传播多个波形信号的相应波形信号，以及组合器，其将来自多个传输线的输出的多个波形信号接收并组合 由输出终端电阻端接输出的组合输出波形信号。 微波电路还包括补偿信号发生器，其产生补偿信号以减轻与通过微波电路的信号的传输相关联的反射。
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公开(公告)号：US20210083676A1
公开(公告)日：2021-03-18
申请号：US17094452
申请日：2020-11-10
申请人： ANNA Y. HERR , QUENTIN P. HERR , RYAN EDWARD CLARKE , HAROLD CLIFTON HEARNE, III , ALEXANDER LOUIS BRAUN , RANDALL M. BURNETT , TIMOTHY CHI-CHAO LEE
发明人： ANNA Y. HERR , QUENTIN P. HERR , RYAN EDWARD CLARKE , HAROLD CLIFTON HEARNE, III , ALEXANDER LOUIS BRAUN , RANDALL M. BURNETT , TIMOTHY CHI-CHAO LEE
IPC分类号： H03K19/195 , G06N10/00 , G11C11/44 , H03K3/38
摘要： Non-destructive read out (NDRO) circuits are provided for use in reciprocal quantum logic (RQL) superconducting systems. Each NDRO circuit includes a “body” circuit that provides a single or multi-state sub-critical bias current to one or many independent “tail” circuitries. Each “tail” has minimal effect on the “body” thereby preventing any interference or destruction to the state of the “body” circuitry. The circuits reduce device count and thereby increase circuit density, simplify and reduce the cost of fabrication, and provide functionality not available in existing designs, such as the ability to write a state and read it in the same operation cycle. The NDRO circuits provide more compact unit cells useful in memory or logic arrays, demanding fewer resources with increased functionality. The circuits also provide compact cells for AND, AND-OR, A-NOT-B, inverter, multiplexer, and demultiplexer gates.
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公开(公告)号：US20160370822A1
公开(公告)日：2016-12-22
申请号：US14746377
申请日：2015-06-22
IPC分类号： G06F1/10
摘要： One embodiment includes a clock distribution system. The system includes a standing-wave resonator configured to receive and to resonate a sinusoidal clock signal. The standing-wave resonator includes at least one anti-node portion associated with a peak current amplitude of the sinusoidal clock signal. The system also includes at least one clock line interconnecting each of the at least one anti-node portion and an associated circuit. The at least one clock line can be configured to propagate the sinusoidal clock signal for timing functions associated with the associated circuit.
摘要翻译： 一个实施例包括时钟分配系统。 该系统包括被配置为接收和谐振正弦时钟信号的驻波谐振器。 驻波共振器包括与正弦时钟信号的峰值电流幅度相关联的至少一个反节点部分。 该系统还包括互连至少一个反节点部分和相关电路中的每一个的至少一个时钟线。 至少一个时钟线可被配置为传播用于与相关电路相关联的定时功能的正弦时钟信号。
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公开(公告)号：US20160013791A1
公开(公告)日：2016-01-14
申请号：US14325518
申请日：2014-07-08
申请人： ANNA Y. HERR , QUENTIN P. HERR
发明人： ANNA Y. HERR , QUENTIN P. HERR
IPC分类号： H03K19/00 , H03K19/195
CPC分类号： H03K19/0008 , B82Y10/00 , G06N99/002 , G11C11/44 , H03K3/38 , H03K19/1952
摘要： One embodiment includes a superconductive gate system. The superconductive gate system includes a Josephson D-gate circuit comprising a bi-stable loop configured to store a digital state as one of a first data state and a second data state in response to an enable single flux quantum (SFQ) pulse provided on an enable input and a respective presence of or absence of a data SFQ pulse provided on a data input. The digital state can be provided at an output. The readout circuit is coupled to the output and can be configured to reproduce the digital state as an output signal.
摘要翻译： 一个实施例包括超导门系统。 超导栅极系统包括约瑟夫森D门电路，其包括双稳态环路，其被配置为响应于在第一数据状态和第二数据状态上提供的使能单通量量子（SFQ）脉冲而将数字状态存储为第一数据状态和第二数据状态之一 启用输入和相应的存在或不存在在数据输入上提供的数据SFQ脉冲。 数字状态可以在输出端提供。 读出电路耦合到输出，并且可以被配置为将数字状态再现为输出信号。
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公开(公告)号：US20200287118A1
公开(公告)日：2020-09-10
申请号：US16296007
申请日：2019-03-07
摘要： Superconducting integrated circuit layouts are proofed against the detrimental effects of stray flux by designing and fabricating them to have one or more ground planes patterned in the x-y plane with a regular grid of low-aspect-ratio flux-trapping voids. The ground plane(s) can be globally patterned with such voids and thousands or more superconducting circuit devices and wires can thereafter be laid out so as not to intersect or come so close to the voids that the trapped flux would induce supercurrents in them, thus preventing undesirable coupling of flux into circuit elements. Sandwiching a wire layer between patterned ground planes permits wires to be laid out even closer to the voids. Voids of successively smaller maximum dimension can be concentrically stacked in pyramidal fashion in multiple ground plane layers having different superconductor transition temperatures, increasing the x-y area available for device placement and wire-up.
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公开(公告)号：US20160267964A1
公开(公告)日：2016-09-15
申请号：US15013687
申请日：2016-02-02
IPC分类号： G11C11/44
摘要： One embodiment describes a memory cell. The memory cell includes a phase hysteretic magnetic Josephson junction (PHMJJ) that is configured to store one of a first binary logic state corresponding to a binary logic-1 state and a second binary logic state corresponding to a binary logic-0 state in response to a write current that is provided to the memory cell and to generate a superconducting phase based on the stored digital state. The memory cell also includes a superconducting read-select device that is configured to implement a read operation in response to a read current that is provided to the memory cell. The memory cell further includes at least one Josephson junction configured to provide an output based on the superconducting phase of the PHMJJ during the read operation, the output corresponding to the stored digital state.
摘要翻译： 一个实施例描述了一个存储单元。 存储器单元包括相滞后磁约瑟夫逊结（PHMJJ），其被配置为存储对应于二进制逻辑1状态的第一二进制逻辑状态和对应于二进制逻辑0状态的第二二进制逻辑状态之一，以响应于 写入电流，其被提供给存储器单元并且基于所存储的数字状态生成超导相位。 存储器单元还包括超导读取选择器件，其被配置为响应于提供给存储器单元的读取电流来实现读取操作。 存储单元还包括至少一个约瑟夫逊结，其被配置为在读取操作期间基于PHMJJ的超导相位提供输出，对应于所存储的数字状态的输出。
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公开(公告)号：US20220393850A1
公开(公告)日：2022-12-08
申请号：US17340814
申请日：2021-06-07
IPC分类号： H04L7/00 , H03K19/195 , G06N10/00 , G06F13/40
摘要： One example includes an isochronous receiver system. The system includes a pulse receiver configured to receive an input data signal from a transmission line and to convert the input data signal to a pulse signal. The system also includes a converter system comprising a phase converter system. The phase converter system includes a plurality of pulse converters associated with a respective plurality of sampling windows across a period of an AC clock signal. At least two of the sampling windows overlap at any given phase of the AC clock signal, such that the converter system is configured to generate an output pulse signal that is phase-aligned with at least one of a plurality of sampling phases of the AC clock signal based on associating the pulse signal with at least two of the sampling windows.
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公开(公告)号：US20200044656A1
公开(公告)日：2020-02-06
申请号：US16051058
申请日：2018-07-31
申请人： ANNA Y. HERR , QUENTIN P. HERR , RYAN EDWARD CLARKE , HAROLD CLIFTON HEARNE, III , ALEXANDER LOUIS BRAUN , RANDALL M. BURNETT , TIMOTHY CHI-CHAO LEE
发明人： ANNA Y. HERR , QUENTIN P. HERR , RYAN EDWARD CLARKE , HAROLD CLIFTON HEARNE, III , ALEXANDER LOUIS BRAUN , RANDALL M. BURNETT , TIMOTHY CHI-CHAO LEE
IPC分类号： H03K19/195 , H03K3/38 , G11C11/44 , G06N99/00
摘要： Non-destructive read out (NDRO) circuits are provided for use in reciprocal quantum logic (RQL) superconducting systems. Each NDRO circuit includes a “body” circuit that provides a single or multi-state sub-critical bias current to one or many independent “tail” circuitries. Each “tail” has minimal effect on the “body” thereby preventing any interference or destruction to the state of the “body” circuitry. The circuits reduce device count and thereby increase circuit density, simplify and reduce the cost of fabrication, and provide functionality not available in existing designs, such as the ability to write a state and read it in the same operation cycle. The NDRO circuits provide more compact unit cells useful in memory or logic arrays, demanding fewer resources with increased functionality. The circuits also provide compact cells for AND, AND-OR, A-NOT-B, inverter, multiplexer, and demultiplexer gates.
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公开(公告)号：US20190245544A1
公开(公告)日：2019-08-08
申请号：US16047883
申请日：2018-07-27
申请人： QUENTIN P. HERR
发明人： QUENTIN P. HERR
IPC分类号： H03K19/195 , G06N10/00
CPC分类号： H03K19/1954 , G06N10/00 , H03K19/1952
摘要： A Josephson inverter gate circuit provides efficient implementation of polarity or logical inversion while eliminating the need for physically large high-efficiency magnetic transformers in the signal path. The circuit can consist of a half-twisted Josephson transmission line (JTL) or a JTL with an unshunted floating Josephson junction that produces two single flux quantum (SFQ) pulses when triggered by an SFQ input signal, which results in an output SFQ signal of reversed polarity. Implemented as a logical inverter, proper initialization of the circuit is accomplished within the signal inversion stage with flux biasing.
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公开(公告)号：US20190196973A1
公开(公告)日：2019-06-27
申请号：US15851264
申请日：2017-12-21
IPC分类号： G06F12/0888 , G11C7/10 , H01L39/22 , G11C11/44 , G06F12/02 , G06F15/80 , G11C11/419 , G06N99/00 , G11C8/08 , G11C8/14
CPC分类号： G06F12/0888 , G06F12/0207 , G06F15/8038 , G06N10/00 , G11C5/02 , G11C7/1012 , G11C7/1015 , G11C7/18 , G11C8/08 , G11C8/10 , G11C8/14 , G11C8/18 , G11C11/005 , G11C11/419 , G11C11/44 , G11C2207/2209 , H01L39/223
摘要： One example includes a memory circuit. The circuit includes a memory array arranged as rows and columns of memory cells. An array portion stores a respective memory word in a given one of the rows in response to a word-write signal corresponding to a write address of the given one of the rows and in response to a plurality of bit-write signals associated with the plurality of columns, and reads a respective memory word from a given one of the rows in response to a word-read signal corresponding to a read address of the given one of the rows and in response to a plurality of bit-read signals associated with the plurality of columns. The circuit also includes a write-through detection system that activates an analog bypass portion to read the memory word from the analog bypass portion in response to the read address being equal to the write address.
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