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105 条记录 (耗时 0.022 秒)

    Linerless shallow trench isolation method
    4.
    发明授权
    Linerless shallow trench isolation method 失效
    无缝浅沟隔离法

    公开(公告)号：US06534379B1

    公开(公告)日：2003-03-18

    申请号：US10051698

    申请日：2002-01-18

    申请人： Philip Fisher ,  Ming-Ren Lin ,  Matthew S. Buynoski

    发明人： Philip Fisher ,  Ming-Ren Lin ,  Matthew S. Buynoski

    IPC分类号： H01L2176

    CPC分类号： H01L21/76264 ,  H01L21/76283

    摘要： A method of making a semiconductor device and a method of isolation of active islands on a silicon-on-insulator semiconductor device, comprising the steps of providing a silicon-on-insulator semiconductor wafer having a silicon active layer, a dielectric isolation layer and a silicon substrate, in which the silicon active layer is formed on the dielectric isolation layer and the dielectric isolation layer is formed on the silicon substrate; forming an isolation trench, the isolation trench defining an active island in the silicon active layer; rounding at least one corner in the active island by application of a high RF bias power high density plasma; and filling the isolation trench with a dielectric trench isolation material by application of a low RF bias power high density plasma. In one embodiment, the rounding step comprises application of a HDP under etching conditions, and the filling step comprises application of a HDP under deposition conditions.

    摘要翻译： 一种制造半导体器件的方法以及在绝缘体上硅半导体器件上隔离有源岛的方法，包括以下步骤：提供具有硅有源层，介电隔离层和绝缘体隔离层的绝缘体上半导体晶片， 在硅衬底上形成硅介质隔离层上的硅有源层和电介质隔离层的硅衬底; 形成隔离沟槽，所述隔离沟槽在所述硅有源层中限定有源岛; 通过应用高RF偏置功率的高密度等离子体使活动岛中的至少一个角落四舍五入; 以及通过施加低RF偏置功率的高密度等离子体，用绝缘沟槽隔离材料填充隔离沟槽。 在一个实施例中，舍入步骤包括在蚀刻条件下施加HDP，并且填充步骤包括在沉积条件下施加HDP。

    Method of forming multiple levels of patterned metallization
    5.
    发明授权
    Method of forming multiple levels of patterned metallization 有权
    形成多层图案化金属化的方法

    公开(公告)号：US06207553B1

    公开(公告)日：2001-03-27

    申请号：US09237258

    申请日：1999-01-26

    申请人： Matthew S. Buynoski ,  Ming-Ren Lin

    发明人： Matthew S. Buynoski ,  Ming-Ren Lin

    IPC分类号： H01L214763

    CPC分类号： H01L21/76885 ,  H01L21/32135

    摘要： Submicron-dimensioned metallization patterns are formed on a substrate surface by a photo-activated selective, anisotropic etching process, wherein selective portions of a metal layer are exposed to collimated UV passing through a pattern of submicron-sized openings in an overlying exposure mask. At least one photo-activatable etching material contained in a gas flowed through the space between the substrate surface and the mask selectively and anisotropically etches the exposed portions of the metal layer in thereby avoiding numerous masking and etching steps as in conventional photolithographic methodology. The inventive method is of particular utility in performing multi-level, in-laid, “back-end” metallization processing of high-density integrated circuit semiconductor devices.

    摘要翻译： 通过光激活的选择性各向异性蚀刻工艺在衬底表面上形成亚微米尺寸的金属化图案，其中金属层的选择部分暴露于准直的UV穿过覆盖的曝光掩模中的亚微米尺寸的开口图案。 包含在通过衬底表面和掩模之间的空间中流动的气体中的至少一种可光致活化的蚀刻材料选择性地并且各向异性地蚀刻金属层的暴露部分，从而避免了如常规光刻方法中的许多掩模和蚀刻步骤。 本发明的方法在执行高密度集成电路半导体器件的多层次的，内置的“后端”金属化处理中是特别有用的。

    Silicon on insulator field effect transistor with heterojunction gate
    6.
    发明授权
    Silicon on insulator field effect transistor with heterojunction gate 有权

    公开(公告)号：US07105421B1

    公开(公告)日：2006-09-12

    申请号：US10835438

    申请日：2004-04-29

    申请人： Qi Xiang ,  Matthew S. Buynoski

    发明人： Qi Xiang ,  Matthew S. Buynoski

    IPC分类号： H01L21/00

    CPC分类号： H01L29/78696 ,  H01L29/432 ,  H01L29/66772 ,  H01L29/78645

    摘要： A field effect transistor (FET) is formed on a silicon on insulator (SOI) substrate in the thin silicon layer above the insulating buried oxide layer. The channel region is lightly doped with a first impurity to increase free carrier conductivity of a first type. The source region and the drain region are heavily dopes with the first impurity. A gate and a back gate are positioned along the side of the channel region and extending from the source region and is implanted with a second semiconductor with an energy gap greater than silicon and is implanted with an impurity to increase free carrier flow of a second type.

    Silicon on insulator field effect transistor with heterojunction gate
    8.
    发明授权
    Silicon on insulator field effect transistor with heterojunction gate 有权
    具有异质结栅的绝缘体上的场效应晶体管

    公开(公告)号：US06759308B2

    公开(公告)日：2004-07-06

    申请号：US09902429

    申请日：2001-07-10

    申请人： Qi Xiang ,  Matthew S. Buynoski

    发明人： Qi Xiang ,  Matthew S. Buynoski

    IPC分类号： H01L2130

    CPC分类号： H01L29/78696 ,  H01L29/432 ,  H01L29/66772 ,  H01L29/78645

    摘要： A field effect transistor (FET) is formed on a silicon on insulator (SOI) substrate in the thin silicon layer above the insulating buried oxide layer. The channel region is lightly doped with a first impurity to increase free carrier conductivity of a first type. The source region and the drain region are heavily dopes with the first impurity. A gate and a back gate are positioned along the side of the channel region and extending from the source region and is implanted with a second semiconductor with an energy gap greater than silicon and is implanted with an impurity to increase free carrier flow of a second type.

    摘要翻译： 在隔离掩埋氧化物层上方的薄硅层中的绝缘体上硅（SOI）衬底上形成场效应晶体管（FET）。 沟道区域被轻掺杂第一杂质以增加第一类型的自由载流子导电性。 源极区和漏极区是具有第一杂质的重掺杂物。 栅极和背栅极沿着沟道区域的侧面定位并且从源极区域延伸并且注入具有大于硅的能隙的第二半导体，并且注入杂质以增加第二类型的自由载流子 。

    Metal gate with PVD amorphous silicon layer having implanted dopants for CMOS devices and method of making with a replacement gate process
    9.
    发明授权
    Metal gate with PVD amorphous silicon layer having implanted dopants for CMOS devices and method of making with a replacement gate process 有权
    具有用于CMOS器件的注入掺杂剂的PVD非晶硅层的金属栅极和用替代栅极工艺制造的方法

    公开(公告)号：US06589866B1

    公开(公告)日：2003-07-08

    申请号：US09691226

    申请日：2000-10-19

    申请人： Paul R. Besser ,  Qi Xiang ,  Matthew S. Buynoski

    发明人： Paul R. Besser ,  Qi Xiang ,  Matthew S. Buynoski

    IPC分类号： H01L2144

    CPC分类号： H01L29/66545 ,  H01L21/28052 ,  H01L29/4933

    摘要： A semiconductor structure and method for making the same provides a metal gate on a silicon substrate. The gate includes a high dielectric constant on the substrate, and a physical vapor deposited (PVD) layer of amorphous silicon on the high k gate dielectric. The metal is then formed on the PVD amorphous silicon layer. Additional dopants are implanted into the PVD amorphous silicon layer. An annealing process forms silicide in the gate, with a layer of silicon remaining unreacted. The work function of the metal gate is substantially the same as a polysilicon gate due to the presence of the PVD amorphous silicon layer, while the additional doping of the PVD amorphous silicon layer lowers the resistivity of the gate electrode.

    摘要翻译： 半导体结构及其制造方法在硅衬底上提供金属栅极。 栅极在衬底上包括高介电常数，以及在高k栅极电介质上的非晶硅的物理气相沉积（PVD）层。 然后在PVD非晶硅层上形成金属。 另外的掺杂剂被注入到PVD非晶硅层中。 退火工艺在栅极中形成硅化物，其中一层硅残留未反应。 由于PVD非晶硅层的存在，金属栅极的功函数与多晶硅栅极基本相同，而PVD非晶硅层的附加掺杂降低了栅电极的电阻率。

    Metal gate with CVD amorphous silicon layer and a barrier layer for CMOS devices and method of making with a replacement gate process
    10.
    发明授权
    Metal gate with CVD amorphous silicon layer and a barrier layer for CMOS devices and method of making with a replacement gate process 失效
    具有CVD非晶硅层的金属栅极和用于CMOS器件的阻挡层以及用替代栅极工艺制造的方法

    公开(公告)号：US06436840B1

    公开(公告)日：2002-08-20

    申请号：US09691188

    申请日：2000-10-19

    申请人： Paul R. Besser ,  Matthew S. Buynoski ,  Qi Xiang

    发明人： Paul R. Besser ,  Matthew S. Buynoski ,  Qi Xiang

    IPC分类号： H01L21302

    CPC分类号： H01L21/28194 ,  H01L21/28044 ,  H01L21/3146 ,  H01L29/4941 ,  H01L29/517 ,  Y10S438/926

    摘要： A semiconductor structure and method for making the same provides a metal gate on a silicon substrate. The gate includes a high dielectric constant on the substrate, and a chemical vapor deposited layer of amorphous silicon on the high k gate dielectric. A barrier is then deposited on the CVD amorphous silicon layer. A metal is then formed on the barrier. The work function of the metal gate is substantially the same as a polysilicon gate due to the presence of the CVD amorphous silicon layer. The work function is preserved by the barrier during subsequent high temperature processing, due to the barrier which prevents interaction between the CVD amorphous silicon layer and the metal, which could otherwise form silicide and change the work function.

    摘要翻译： 半导体结构及其制造方法在硅衬底上提供金属栅极。 该栅极包括在该基板上的高介电常数和在该高k栅极电介质上的非晶硅化学气相沉积层。 然后在CVD非晶硅层上沉积阻挡层。 然后在屏障上形成金属。 由于CVD非晶硅层的存在，金属栅极的功函数与多晶硅栅极基本相同。 由于防止CVD非晶硅层与金属之间的相互作用的屏障，因此在随后的高温处理期间，阻挡层保留功函数，否则可能形成硅化物并改变功函数。