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    Metal gate with CVD amorphous silicon layer and silicide for CMOS devices and method of making with a replacement gate process
    2.
    发明授权
    Metal gate with CVD amorphous silicon layer and silicide for CMOS devices and method of making with a replacement gate process 失效
    具有CVD非晶硅层的金属栅极和用于CMOS器件的硅化物和用替代栅极工艺制造的方法

    公开(公告)号：US06440868B1

    公开(公告)日：2002-08-27

    申请号：US09691259

    申请日：2000-10-19

    申请人： Paul R. Besser ,  Qi Xiang ,  Matthew S. Buynoski

    发明人： Paul R. Besser ,  Qi Xiang ,  Matthew S. Buynoski

    IPC分类号： H01L21302

    CPC分类号： H01L21/28052 ,  H01L29/517 ,  H01L29/66545 ,  Y10S438/926

    摘要： A semiconductor structure and method for making the same provides a metal gate on a silicon substrate. The gate includes a high dielectric constant on the substrate, and a chemical vapor deposited layer of amorphous silicon on the high k gate dielectric. The metal is then deposited on the CVD amorphous silicon layer. An annealing process forms silicide in the gate, with a layer of silicon remaining unreacted. The work function of the metal gate is substantially the same as a polysilicon gate due to the presence of the CVD amorphous silicon layer.

    摘要翻译： 半导体结构及其制造方法在硅衬底上提供金属栅极。 该栅极包括在该基板上的高介电常数和在该高k栅极电介质上的非晶硅化学气相沉积层。 然后将金属沉积在CVD非晶硅层上。 退火工艺在栅极中形成硅化物，其中一层硅残留未反应。 由于CVD非晶硅层的存在，金属栅极的功函数与多晶硅栅极基本相同。

    Reduction of metal silicide/silicon interface roughness by dopant implantation processing
    3.
    发明授权
    Reduction of metal silicide/silicon interface roughness by dopant implantation processing 有权
    通过掺杂剂注入处理减少金属硅化物/硅界面粗糙度

    公开(公告)号：US06376343B1

    公开(公告)日：2002-04-23

    申请号：US09812695

    申请日：2001-03-21

    申请人： Matthew S. Buynoski ,  Paul R. Besser ,  Qi Xiang

    发明人： Matthew S. Buynoski ,  Paul R. Besser ,  Qi Xiang

    IPC分类号： H01L21425

    CPC分类号： H01L29/6659 ,  H01L21/26513 ,  H01L21/28518 ,  H01L21/823814 ,  H01L29/665

    摘要： Deleterious roughness of metal silicide/doped Si interfaces arising during conventional salicide processing for forming shallow-depth source and drain junction regions of MOS transistors and/or CMOS devices due to poor compatibility of particular dopants and metal suicides is avoided, or at least substantially reduced, by implanting a first (main) dopant species having relatively good compatibility with the metal silicide, such that the maximum concentration thereof is at a depth above the depth to which silicidation reaction occurs and implanting a second (auxiliary) dopant species having relatively poor compatibility with the metal silicide, wherein the maximum concentration thereof is less than that of the first (main) dopant and is at a depth below the depth to which silicidation reaction occurs. The invention enjoys particular utility in forming NiSi layers on As-doped Si substrates.

    摘要翻译： 避免了由于特定掺杂剂和金属硅化物的不良相容性而形成浅晶体管和/或CMOS器件的浅深度源极和漏极结区域的常规自对准硅化物处理期间产生的金属硅化物/掺杂Si界面的有缺陷的粗糙度，或至少大大降低 通过植入与金属硅化物具有相对良好的相容性的第一（主要）掺杂剂物质，使得其最大浓度在高于发生硅化反应的深度的深度处，并且注入具有相对较差相容性的第二（辅助）掺杂剂种类 金属硅化物，其中其最大浓度小于第一（主要）掺杂剂的最大浓度，并且处于低于发生硅化反应的深度的深度。 本发明特别适用于在掺杂Si的衬底上形成NiSi层。

    Silicon on insulator field effect transistor with heterojunction gate
    5.
    发明授权
    Silicon on insulator field effect transistor with heterojunction gate 有权

    公开(公告)号：US07105421B1

    公开(公告)日：2006-09-12

    申请号：US10835438

    申请日：2004-04-29

    申请人： Qi Xiang ,  Matthew S. Buynoski

    发明人： Qi Xiang ,  Matthew S. Buynoski

    IPC分类号： H01L21/00

    CPC分类号： H01L29/78696 ,  H01L29/432 ,  H01L29/66772 ,  H01L29/78645

    摘要： A field effect transistor (FET) is formed on a silicon on insulator (SOI) substrate in the thin silicon layer above the insulating buried oxide layer. The channel region is lightly doped with a first impurity to increase free carrier conductivity of a first type. The source region and the drain region are heavily dopes with the first impurity. A gate and a back gate are positioned along the side of the channel region and extending from the source region and is implanted with a second semiconductor with an energy gap greater than silicon and is implanted with an impurity to increase free carrier flow of a second type.

    Silicon on insulator field effect transistor with heterojunction gate
    7.
    发明授权
    Silicon on insulator field effect transistor with heterojunction gate 有权
    具有异质结栅的绝缘体上的场效应晶体管

    公开(公告)号：US06759308B2

    公开(公告)日：2004-07-06

    申请号：US09902429

    申请日：2001-07-10

    申请人： Qi Xiang ,  Matthew S. Buynoski

    发明人： Qi Xiang ,  Matthew S. Buynoski

    IPC分类号： H01L2130

    CPC分类号： H01L29/78696 ,  H01L29/432 ,  H01L29/66772 ,  H01L29/78645

    摘要： A field effect transistor (FET) is formed on a silicon on insulator (SOI) substrate in the thin silicon layer above the insulating buried oxide layer. The channel region is lightly doped with a first impurity to increase free carrier conductivity of a first type. The source region and the drain region are heavily dopes with the first impurity. A gate and a back gate are positioned along the side of the channel region and extending from the source region and is implanted with a second semiconductor with an energy gap greater than silicon and is implanted with an impurity to increase free carrier flow of a second type.

    摘要翻译： 在隔离掩埋氧化物层上方的薄硅层中的绝缘体上硅（SOI）衬底上形成场效应晶体管（FET）。 沟道区域被轻掺杂第一杂质以增加第一类型的自由载流子导电性。 源极区和漏极区是具有第一杂质的重掺杂物。 栅极和背栅极沿着沟道区域的侧面定位并且从源极区域延伸并且注入具有大于硅的能隙的第二半导体，并且注入杂质以增加第二类型的自由载流子 。

    Metal gate with PVD amorphous silicon layer having implanted dopants for CMOS devices and method of making with a replacement gate process
    8.
    发明授权
    Metal gate with PVD amorphous silicon layer having implanted dopants for CMOS devices and method of making with a replacement gate process 有权
    具有用于CMOS器件的注入掺杂剂的PVD非晶硅层的金属栅极和用替代栅极工艺制造的方法

    公开(公告)号：US06589866B1

    公开(公告)日：2003-07-08

    申请号：US09691226

    申请日：2000-10-19

    申请人： Paul R. Besser ,  Qi Xiang ,  Matthew S. Buynoski

    发明人： Paul R. Besser ,  Qi Xiang ,  Matthew S. Buynoski

    IPC分类号： H01L2144

    CPC分类号： H01L29/66545 ,  H01L21/28052 ,  H01L29/4933

    摘要： A semiconductor structure and method for making the same provides a metal gate on a silicon substrate. The gate includes a high dielectric constant on the substrate, and a physical vapor deposited (PVD) layer of amorphous silicon on the high k gate dielectric. The metal is then formed on the PVD amorphous silicon layer. Additional dopants are implanted into the PVD amorphous silicon layer. An annealing process forms silicide in the gate, with a layer of silicon remaining unreacted. The work function of the metal gate is substantially the same as a polysilicon gate due to the presence of the PVD amorphous silicon layer, while the additional doping of the PVD amorphous silicon layer lowers the resistivity of the gate electrode.

    摘要翻译： 半导体结构及其制造方法在硅衬底上提供金属栅极。 栅极在衬底上包括高介电常数，以及在高k栅极电介质上的非晶硅的物理气相沉积（PVD）层。 然后在PVD非晶硅层上形成金属。 另外的掺杂剂被注入到PVD非晶硅层中。 退火工艺在栅极中形成硅化物，其中一层硅残留未反应。 由于PVD非晶硅层的存在，金属栅极的功函数与多晶硅栅极基本相同，而PVD非晶硅层的附加掺杂降低了栅电极的电阻率。

    Metal gate with CVD amorphous silicon layer and a barrier layer for CMOS devices and method of making with a replacement gate process
    10.
    发明授权
    Metal gate with CVD amorphous silicon layer and a barrier layer for CMOS devices and method of making with a replacement gate process 失效
    具有CVD非晶硅层的金属栅极和用于CMOS器件的阻挡层以及用替代栅极工艺制造的方法

    公开(公告)号：US06436840B1

    公开(公告)日：2002-08-20

    申请号：US09691188

    申请日：2000-10-19

    申请人： Paul R. Besser ,  Matthew S. Buynoski ,  Qi Xiang

    发明人： Paul R. Besser ,  Matthew S. Buynoski ,  Qi Xiang

    IPC分类号： H01L21302

    CPC分类号： H01L21/28194 ,  H01L21/28044 ,  H01L21/3146 ,  H01L29/4941 ,  H01L29/517 ,  Y10S438/926

    摘要： A semiconductor structure and method for making the same provides a metal gate on a silicon substrate. The gate includes a high dielectric constant on the substrate, and a chemical vapor deposited layer of amorphous silicon on the high k gate dielectric. A barrier is then deposited on the CVD amorphous silicon layer. A metal is then formed on the barrier. The work function of the metal gate is substantially the same as a polysilicon gate due to the presence of the CVD amorphous silicon layer. The work function is preserved by the barrier during subsequent high temperature processing, due to the barrier which prevents interaction between the CVD amorphous silicon layer and the metal, which could otherwise form silicide and change the work function.

    摘要翻译： 半导体结构及其制造方法在硅衬底上提供金属栅极。 该栅极包括在该基板上的高介电常数和在该高k栅极电介质上的非晶硅化学气相沉积层。 然后在CVD非晶硅层上沉积阻挡层。 然后在屏障上形成金属。 由于CVD非晶硅层的存在，金属栅极的功函数与多晶硅栅极基本相同。 由于防止CVD非晶硅层与金属之间的相互作用的屏障，因此在随后的高温处理期间，阻挡层保留功函数，否则可能形成硅化物并改变功函数。