公开(公告)号：US10205006B2

公开(公告)日：2019-02-12

申请号：US15951552

申请日：2018-04-12

Applicant: Renesas Electronics Corporation

Inventor： Atsushi Amo

IPC: H01L29/66 ,  H01L29/792 ,  H01L27/11568 ,  H01L27/06 ,  H01L23/522 ,  H01L29/40 ,  H01L27/11582 ,  H01L49/02

Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor substrate including a main surface, the main surface including a first area and a second area, which is different from the first area in a plan view, forming a first trench in the main surface of the semiconductor substrate in the first area, after the forming the first trench, forming a first insulating film on a side wall surface and a bottom face of the first trench, and after the forming the first insulating film, forming a first conductor film over the semiconductor substrate in the first area and a second area to embed a portion of the first conductor film into the first trench through the first insulating film.

公开(公告)号：US09755086B2

公开(公告)日：2017-09-05

申请号：US15011510

申请日：2016-01-30

Applicant: Renesas Electronics Corporation

Inventor： Atsushi Amo

IPC: H01L29/792 ,  H01L29/94 ,  H01L29/66 ,  H01L29/423 ,  H01L27/06 ,  H01L27/11573 ,  G11C16/04

CPC classification number: H01L29/945 ,  G11C16/0466 ,  H01L27/0629 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/66181 ,  H01L29/66833 ,  H01L29/792

Abstract: In a semiconductor device including a split gate type MONOS memory, and a trench capacitor element having an upper electrode partially embedded in trenches formed in the main surface of a semiconductor substrate, merged therein, the flatness of the top surface of the upper electrode embedded in the trench is improved. The polysilicon film formed over the semiconductor substrate to form a control gate electrode forming a memory cell of the MONOS memory is embedded in the trenches formed in the main surface of the semiconductor substrate in a capacitor element formation region, thereby to form the upper electrode including the polysilicon film in the trenches.

公开(公告)号：US11563111B2

公开(公告)日：2023-01-24

申请号：US16928854

申请日：2020-07-14

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Atsushi Amo

IPC: H01L29/66 ,  H01L21/28

Abstract: A trench is formed by removing a portion of each of the charge accumulation film and the insulating film located between the control gate electrode and the memory gate electrode. The insulating film is formed in the trench so that the upper surface of each of the insulating film and the charge accumulation film is covered with the insulating film. When exposing the upper surface of the control gate electrode and the memory gate electrode, the upper surface of each of the insulating film and the charge accumulation film is not exposed.

公开(公告)号：US20170278954A1

公开(公告)日：2017-09-28

申请号：US15417050

申请日：2017-01-26

Applicant: Renesas Electronics Corporation

Inventor： Atsushi Amo

IPC: H01L29/66 ,  H01L29/40 ,  H01L27/06 ,  H01L23/522 ,  H01L29/792 ,  H01L27/11568

CPC classification number: H01L29/66833 ,  H01L23/5223 ,  H01L27/0629 ,  H01L27/11568 ,  H01L27/11582 ,  H01L28/00 ,  H01L29/401 ,  H01L29/66545 ,  H01L29/792

Abstract: To reduce a manufacturing cost of a semiconductor device in which a high breakdown voltage transistor and a trench capacitive element in which a part of an upper electrode is embedded in a trench formed in a main surface of a semiconductor substrate are mixed together.After an insulating film is formed over a main surface of a semiconductor substrate so as to cover a trench formed in the main surface of the semiconductor substrate, the insulating film is processed to form an upper electrode of a capacitive element, a gate insulating film which insulates the semiconductor substrate to be a lower electrode, and a gate insulting film of a high breakdown voltage transistor.

公开(公告)号：US09947776B2

公开(公告)日：2018-04-17

申请号：US15417050

申请日：2017-01-26

Applicant: Renesas Electronics Corporation

Inventor： Atsushi Amo

IPC: H01L21/8242 ,  H01L29/66 ,  H01L29/792 ,  H01L27/11568 ,  H01L27/06 ,  H01L23/522 ,  H01L29/40

CPC classification number: H01L29/66833 ,  H01L23/5223 ,  H01L27/0629 ,  H01L27/11568 ,  H01L27/11582 ,  H01L28/00 ,  H01L29/401 ,  H01L29/66545 ,  H01L29/792

Abstract: To reduce a manufacturing cost of a semiconductor device in which a high breakdown voltage transistor and a trench capacitive element in which a part of an upper electrode is embedded in a trench formed in a main surface of a semiconductor substrate are mixed together.After an insulating film is formed over a main surface of a semiconductor substrate so as to cover a trench formed in the main surface of the semiconductor substrate, the insulating film is processed to form an upper electrode of a capacitive element, a gate insulating film which insulates the semiconductor substrate to be a lower electrode, and a gate insulting film of a high breakdown voltage transistor.

公开(公告)号：US12040399B2

公开(公告)日：2024-07-16

申请号：US17697393

申请日：2022-03-17

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Eiji Tsukuda ,  Tohru Kawai ,  Atsushi Amo

IPC: H01L29/51 ,  H01L29/78

CPC classification number: H01L29/78391 ,  H01L29/516

Abstract: A semiconductor device is provided with an SOI substrate which includes a semiconductor substrate, a ferroelectric layer and a semiconductor layer, and has a first region in which a first MISFET is formed. The first MISFET includes: the semiconductor substrate in the first region; the ferroelectric layer in the first region; the semiconductor layer in the first region; a first gate insulating film formed on the semiconductor layer in the first region; a first gate electrode formed on the first gate insulating film; a first source region located on one side of the first gate electrode and formed in the semiconductor layer in the first region; and a first drain region located on the other side of the first gate electrode and formed in the semiconductor layer in the first region.

公开(公告)号：US10243085B2

公开(公告)日：2019-03-26

申请号：US15658259

申请日：2017-07-24

Applicant: Renesas Electronics Corporation

Inventor： Atsushi Amo

IPC: H01L29/792 ,  H01L29/66 ,  H01L29/78 ,  H01L21/28 ,  H01L29/423 ,  H01L27/1157

Abstract: An object is to provide a reliability-improved semiconductor device having a MONOS memory that rewrites data by injecting carriers into a charge storage portion. When a memory gate electrode having a small gate length is formed in order to overlap a carrier injection position in write operation with that in erase operation, each into an ONO film including a charge storage portion, the ONO film is formed in a recess of a main surface of a semiconductor substrate for securing a large channel length. In a step of manufacturing this structure, control gate electrodes are formed by stepwise processing of a polysilicon film by first and second etching and then, the recess is formed in the main surface of the semiconductor substrate on one side of the control gate electrode by second etching.

公开(公告)号：US10211348B2

公开(公告)日：2019-02-19

申请号：US15914196

申请日：2018-03-07

Applicant: Renesas Electronics Corporation

Inventor： Atsushi Amo

IPC: H01L29/94 ,  H01L27/06 ,  H01L29/66 ,  H01L29/423 ,  H01L27/11573 ,  G11C16/04 ,  H01L29/792

Abstract: In a semiconductor device including a split gate type MONOS memory, and a trench capacitor element having an upper electrode partially embedded in trenches formed in the main surface of a semiconductor substrate, merged therein, the flatness of the top surface of the upper electrode embedded in the trench is improved. The polysilicon film formed over the semiconductor substrate to form a control gate electrode forming a memory cell of the MONOS memory is embedded in the trenches formed in the main surface of the semiconductor substrate in a capacitor element formation region, thereby to form the upper electrode including the polysilicon film in the trenches.

公开(公告)号：US09954120B2

公开(公告)日：2018-04-24

申请号：US15661649

申请日：2017-07-27

Applicant: Renesas Electronics Corporation

Inventor： Atsushi Amo

IPC: H01L29/94 ,  H01L29/792 ,  G11C16/04 ,  H01L27/11573 ,  H01L29/66 ,  H01L29/423 ,  H01L27/06

CPC classification number: H01L29/945 ,  G11C16/0466 ,  H01L27/0629 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/66181 ,  H01L29/66833 ,  H01L29/792

Abstract: In a semiconductor device including a split gate type MONOS memory, and a trench capacitor element having an upper electrode partially embedded in trenches formed in the main surface of a semiconductor substrate, merged therein, the flatness of the top surface of the upper electrode embedded in the trench is improved. The polysilicon film formed over the semiconductor substrate to form a control gate electrode forming a memory cell of the MONOS memory is embedded in the trenches formed in the main surface of the semiconductor substrate in a capacitor element formation region, thereby to form the upper electrode including the polysilicon film in the trenches.

公开(公告)号：US09748407B2

公开(公告)日：2017-08-29

申请号：US15043569

申请日：2016-02-14

Applicant: Renesas Electronics Corporation

Inventor： Atsushi Amo

IPC: H01L21/28 ,  H01L29/792 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L27/1157

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L27/1157 ,  H01L29/42344 ,  H01L29/66484 ,  H01L29/66833 ,  H01L29/7831

Abstract: An object is to provide a reliability-improved semiconductor device having a MONOS memory that rewrites data by injecting carriers into a charge storage portion. When a memory gate electrode having a small gate length is formed in order to overlap a carrier injection position in write operation with that in erase operation, each into an ONO film including a charge storage portion, the ONO film is formed in a recess of a main surface of a semiconductor substrate for securing a large channel length. In a step of manufacturing this structure, control gate electrodes are formed by stepwise processing of a polysilicon film by first and second etching and then, the recess is formed in the main surface of the semiconductor substrate on one side of the control gate electrode by second etching.