公开(公告)号：US09166612B2

公开(公告)日：2015-10-20

申请号：US14336073

申请日：2014-07-21

Applicant: Renesas Electronics Corporation

Inventor： Masaki Fujiwara ,  Yasuo Morimoto ,  Takashi Matsumoto

IPC: H03M1/38 ,  H03M1/12 ,  H03M1/46 ,  H03K5/13 ,  H03K5/00

CPC classification number: H03M1/125 ,  H03K5/133 ,  H03K2005/00065 ,  H03M1/12 ,  H03M1/38 ,  H03M1/46 ,  H03M1/462 ,  H03M1/468

Abstract: To provide a semiconductor device capable of accurately controlling the cycle of an internal clock signal. This semiconductor device, by using signal that is output from a sequence register of an asynchronous successive approximation type ADC when N times of comparison are completed, detects whether or not the signal and its delay signal are output when the period transitions from a comparison period to a sampling period, and generates, on the basis of the detection result, a delay control signal for controlling the cycle of an internal clock signal by controlling the delay times of the delay circuits.

Abstract translation: 提供能够精确地控制内部时钟信号的周期的半导体器件。 当N次比较完成时，通过使用从异步逐次逼近型ADC的序列寄存器输出的信号来完成该半导体器件，当该周期从比较期间过渡到...时，检测信号及其延迟信号是否被输出 并根据检测结果生成用于通过控制延迟电路的延迟时间来控制内部时钟信号的周期的延迟控制信号。

公开(公告)号：US11415666B2

公开(公告)日：2022-08-16

申请号：US16585924

申请日：2019-09-27

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takashi Oshima ,  Tetsuo Matsui ,  Mitsuya Fukazawa ,  Katsuki Tateyama ,  Masaki Fujiwara

IPC: G01S7/35 ,  H03M3/00 ,  G01S13/34

Abstract: A MASH type sigma delta AD converter includes a modulator, an analog filter filtering an extraction signal obtained by extracting a probe signal and an quantization error generated in a quantizer within a sigma delta modulator, a low speed AD converter performing an AD conversion of an output signal of the analog filter, a first adaptive filter searching for a transfer function of the sigma delta modulator, a second adaptive filter searching for a transfer function from an output of the modulator to the low speed AD converter via the analog filter, and a noise cancellation circuit cancelling the probe signal and the quantization error included in an output signal of the quantizer using the search results by the first and second adaptive filters.

公开(公告)号：US09559716B1

公开(公告)日：2017-01-31

申请号：US15197447

申请日：2016-06-29

Applicant: Renesas Electronics Corporation

Inventor： Tetsuo Matsui ,  Hiroto Suzuki ,  Masaki Fujiwara ,  Tetsuro Matsuno

IPC: H03M1/06 ,  H03M1/46 ,  H03M1/12

CPC classification number: H03M1/46 ,  H03M1/069 ,  H03M1/1061 ,  H03M1/124 ,  H03M1/468

Abstract: A processing speed can be improved while the accuracy of AD conversion is enhanced. An AD converter includes: a higher-order DAC that samples an analog input signal and performs DA conversion corresponding to higher-order bits of a digital output signal; an extension DAC that performs DA conversion to positive and negative polarities on an extension bit for expanding bits of the higher-order DAC; a lower-order DAC that performs DA conversion corresponding to lower-order bits of the digital output signal; a comparator that compares a comparison reference voltage with output voltages of the higher-order DAC, the extension DAC, and the lower-order DAC; and a successive approximation logic that controls successive approximation performed by the higher-order DAC, the extension DAC, and the lower-order DAC based on a comparison result of the comparator and generates the digital output signal.

Abstract translation: 可以提高处理速度，同时提高AD转换的精度。 AD转换器包括：高阶DAC，其对模拟输入信号进行采样，并对数字输出信号的高位进行DA转换; 扩展DAC，用于在用于扩展高阶DAC的位的扩展位上执行DA转换为正极性和负极性; 执行对应于数字输出信号的低阶位的DA转换的低阶DAC; 将比较参考电压与高阶DAC，扩展DAC和低阶DAC的输出电压进行比较的比较器; 以及基于比较器的比较结果控制由高阶DAC，扩展DAC和低阶DAC执行的逐次逼近的逐次逼近逻辑，并产生数字输出信号。