公开(公告)号：US12272592B2

公开(公告)日：2025-04-08

申请号：US18664656

申请日：2024-05-15

Applicant: Richtek Technology Corporation

Inventor： Kun-Huang Yu ,  Chien-Yu Chen ,  Ting-Wei Liao ,  Chih-Wen Hsiung ,  Chun-Lung Chang ,  Kuo-Chin Chiu ,  Wu-Te Weng ,  Chien-Wei Chiu ,  Yong-Zhong Hu ,  Ta-Yung Yang

IPC: H01L21/762 ,  H10D30/65 ,  H10D62/10 ,  H10D64/27

Abstract: A high voltage device includes: a semiconductor layer, a well, a bulk region, a gate, a source, and a drain. The bulk region is formed in the semiconductor layer and contacts the well region along a channel direction. A portion of the bulk region is vertically below and in contact with the gate, to provide an inversion region of the high voltage device when the high voltage device is in conductive operation. A portion of the well lies between the bulk region and the drain, to separate the bulk region from the drain. A first concentration peak region of an impurities doping profile of the bulk region is vertically below and in contact with the source. A concentration of a second conductivity type impurities of the first concentration peak region is higher than that of other regions in the bulk region.

公开(公告)号：US20230197725A1

公开(公告)日：2023-06-22

申请号：US18052950

申请日：2022-11-07

Applicant: Richtek Technology Corporation

Inventor： Wu-Te Weng ,  Chih-Wen Hsiung ,  Ta-Yung Yang

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/0922 ,  H01L27/0928 ,  H01L21/823857 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/823892 ,  H01L21/823814

Abstract: An integrated structure of CMOS devices includes: a semiconductor layer, insulation regions, a first high voltage P-type well and a second high voltage P-type well, a first high voltage N-type well and a second high voltage N-type well, a first low voltage P-type well and a second low voltage P-type well, a first low voltage N-type well and a second low voltage N-type well, and eight gates. A CMOS device having an ultra high threshold voltage is formed in ultra high threshold device region; a CMOS device having a high threshold voltage is formed in high threshold device region; a CMOS device having a middle threshold voltage is formed in the middle threshold device region; and a CMOS device having a low threshold voltage is formed in the low threshold device region.

公开(公告)号：US20220336588A1

公开(公告)日：2022-10-20

申请号：US17718101

申请日：2022-04-11

Applicant: Richtek Technology Corporation

Inventor： Chih-Wen Hsiung ,  Chun-Lung Chang ,  Kun-Huang Yu ,  Kuo-Chin Chiu ,  Wu-Te Weng

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/78 ,  H01L21/74 ,  H01L29/66

Abstract: A high voltage device includes: a semiconductor layer, a well, a body region, a body contact, a gate, a source, and a drain. The body cofntact is configured as an electrical contact of the body region. The body contact and the source overlap with each other to define an overlap region. The body contact has a depth from an upper surface of the semiconductor layer, wherein the depth is deeper than a depth of the source, whereby a part of the body contact is located vertically below the overlap region. A length of the overlap region in a channel direction is not shorter than a predetermined length, so as to suppress a parasitic bipolar junction transistor from being turning on when the high voltage device operates, wherein the parasitic bipolar junction transistor is formed by a part of the well, a part of the body region and a part of the source.

公开(公告)号：US20220157982A1

公开(公告)日：2022-05-19

申请号：US17506422

申请日：2021-10-20

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Kuo-Chin Chiu ,  Ta-Yung Yang ,  Chien-Wei Chiu ,  Wu-Te Weng ,  Chien-Yu Chen ,  Chih-Wen Hsiung ,  Chun-Lung Chang ,  Kun-Huang Yu ,  Ting-Wei Liao

IPC: H01L29/78 ,  H01L29/872 ,  H01L29/66

Abstract: A high voltage device for use as an up-side switch of a power stage circuit includes: at least one lateral diffused metal oxide semiconductor (LDMOS) device, a second conductivity type isolation region and at least one Schottky barrier diode (SBD). The LDMOS device includes: a well formed in a semiconductor layer, a body region, a gate, a source and a drain. The second conductivity type isolation region is formed in the semiconductor layer and is electrically connected to the body region. The SBD includes: a Schottky metal layer formed on the semiconductor layer and a Schottky semiconductor layer formed in the semiconductor layer. The Schottky semiconductor layer and the Schottky metal layer form a Schottky contact. In the semiconductor layer, the Schottky semiconductor layer is adjacent to and in contact with the second conductivity type isolation region.

公开(公告)号：US20230178648A1

公开(公告)日：2023-06-08

申请号：US17983434

申请日：2022-11-09

Applicant: Richtek Technology Corporation

Inventor： Chih-Wen Hsiung ,  Wu-Te Weng ,  Ta-Yung Yang

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/7816 ,  H01L29/42368 ,  H01L29/7835 ,  H01L29/66659 ,  H01L29/1095

Abstract: An NMOS half-bridge power device includes: a semiconductor layer, a plurality of insulation regions, a first N-type high voltage well and a second N-type high voltage well, which are formed by one same ion implantation process, a first P-type high voltage well and a second P-type high voltage well, which are formed by one same ion implantation process, a first drift oxide region and a second drift oxide region, which are formed by one same etch process including etching a drift oxide layer; a first gate and a second gate, which are formed by one same etch process including etching a poly silicon layer, a first P-type body region and a second P-type body region, which are formed by one same ion implantation process, a first N-type source and a first N-type drain, and a second N-type source and a second N-type drain.

公开(公告)号：US20230178438A1

公开(公告)日：2023-06-08

申请号：US17981387

申请日：2022-11-05

Applicant: Richtek Technology Corporation

Inventor： Wu-Te Weng ,  Chih-Wen Hsiung ,  Ta-Yung Yang

IPC: H01L21/8234

CPC classification number: H01L21/823481 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823462

Abstract: An integration manufacturing method of a depletion high voltage NMOS device and a depletion low voltage NMOS device includes: providing a substrate; forming a semiconductor layer on the substrate; forming insulation regions on the semiconductor layer; forming an N-type well in the depletion high voltage NMOS device region; forming a high voltage P-type well in the semiconductor layer, wherein the N-type well and the high voltage P-type well are in contact with each other in a channel direction; forming an oxide layer on the semiconductor layer after the N-type well and the high voltage P-type well formed; forming a low voltage P-type well; and forming an N-type high voltage channel region and an N-type low voltage channel region, such that each of the depletion high voltage NMOS device and the depletion low voltage NMOS device is turned ON when a gate-source voltage thereof is zero voltage.

公开(公告)号：US20230170262A1

公开(公告)日：2023-06-01

申请号：US17858167

申请日：2022-07-06

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Chih-Wen Hsiung ,  Wu-Te Weng ,  Ta-Yung Yang

IPC: H01L21/8234

CPC classification number: H01L21/823493 ,  H01L21/823456

Abstract: An integration manufacturing method of a high voltage device and a low voltage device includes: providing a substrate; forming a semiconductor layer on the substrate; forming insulation regions on the semiconductor layer, for defining a high voltage device region and a low voltage device region; forming a first high voltage well in the high voltage device region; forming a second high voltage well in the semiconductor layer, wherein the first high voltage well and the second high voltage well are in contact with each other in a channel direction; forming an oxide layer on the semiconductor layer, wherein the oxide layer overlays the high voltage device region and the low voltage device region; and forming a first low voltage well in the low voltage device region in the semiconductor layer.

公开(公告)号：US20220223733A1

公开(公告)日：2022-07-14

申请号：US17547707

申请日：2021-12-10

Applicant: Richtek Technology Corporation

Inventor： Chun-Lung Chang ,  Chih-Wen Hsiung ,  Kun-Huang Yu ,  Kuo-Chin Chiu ,  Wu-Te Weng ,  Chien-Wei Chiu ,  Ta-Yung Yang

IPC: H01L29/78 ,  H01L29/66

Abstract: A high voltage device includes: a semiconductor layer, a well region, a shallow trench isolation region, a drift oxide region, a body region, a gate, a source, and a drain. The drift oxide region is located on a drift region. The shallow trench isolation region is located below the drift oxide region. A part of the drift oxide region is located vertically above a part of the shallow trench isolation region and is in contact with the shallow trench isolation region. The shallow trench isolation region is formed between the drain and the body region.

公开(公告)号：US20210074851A1

公开(公告)日：2021-03-11

申请号：US16868456

申请日：2020-05-06

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Chien-Wei Chiu ,  Ta-Yung Yang ,  Wu-Te Weng ,  Chien-Yu Chen ,  Kun-Huang Yu ,  Chih-Wen Hsiung ,  Kuo-Chin Chiu ,  Chun-Lung Chang

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/40 ,  H01L21/765 ,  H01L29/66

Abstract: The present invention provides a high voltage device and a manufacturing method thereof. The high voltage device includes: a semiconductor layer, a drift oxide region, a well, a body region, a gate, at least one sub-gate, a source, and a drain. The drift oxide region is located on a drift region in an operation region. The sub-gate is formed on the drift oxide region right above the drift region. The sub-gate is parallel with the gate. A conductive layer of the gate has a first conductivity type, and a conductive layer of the sub-gate has a second conductivity type or is an intrinsic semiconductor structure.

公开(公告)号：US12136650B2

公开(公告)日：2024-11-05

申请号：US17718101

申请日：2022-04-11

Applicant: Richtek Technology Corporation

Inventor： Chih-Wen Hsiung ,  Chun-Lung Chang ,  Kun-Huang Yu ,  Kuo-Chin Chiu ,  Wu-Te Weng

IPC: H01L29/78 ,  H01L21/74 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66

Abstract: A high voltage device includes: a semiconductor layer, a well, a body region, a body contact, a gate, a source, and a drain. The body contact is configured as an electrical contact of the body region. The body contact and the source overlap with each other to define an overlap region. The body contact has a depth from an upper surface of the semiconductor layer, wherein the depth is deeper than a depth of the source, whereby a part of the body contact is located vertically below the overlap region. A length of the overlap region in a channel direction is not shorter than a predetermined length, so as to suppress a parasitic bipolar junction transistor from being turning on when the high voltage device operates, wherein the parasitic bipolar junction transistor is formed by a part of the well, a part of the body region and a part of the source.