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    Microcontroller instruction set
    1.
    发明授权
    Microcontroller instruction set 有权
    微控制器指令集

    公开(公告)号：US06708268B1

    公开(公告)日：2004-03-16

    申请号：US09280112

    申请日：1999-03-26

    Applicant: Edward Brian Boles ,  Rodney Drake ,  Darrel Johansen ,  Sumit Mitra ,  Joseph Triece ,  Randy Yach

    Inventor： Edward Brian Boles ,  Rodney Drake ,  Darrel Johansen ,  Sumit Mitra ,  Joseph Triece ,  Randy Yach

    IPC: G06F1208

    CPC classification number: G06F9/30192 ,  G06F9/30032 ,  G06F9/3004 ,  G06F9/30101 ,  G06F9/3012 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30167 ,  G06F9/321 ,  G06F9/325

    Abstract: A microcontroller apparatus is provided with an instruction set for manipulating the behavior of the microcontroller. The apparatus and system is provided that enables a linearized address space that makes modular emulation possible. Direct or indirect addressing is possible through register files or data memory. Special function registers, including the Program Counter (PC) and Working Register (W), are mapped in the data memory. An orthogonal (symmetrical) instruction set makes possible any operation on any register using any addressing mode. Consequently, two file registers to be used in some two operand instructions. This allows data to be moved directly between two registers without going through the W register. Thus increasing performance and decreasing program memory usage.

    Abstract translation: 微控制器装置设置有用于操纵微控制器的行为的指令集。 提供了使得能够实现模块化仿真的线性化地址空间的装置和系统。 可以通过寄存器文件或数据存储器进行直接或间接寻址。 特殊功能寄存器，包括程序计数器（PC）和工作寄存器（W），映射到数据存储器中。 正交（对称）指令集可以使用任何寻址模式对任何寄存器进行任何操作。 因此，在两个操作数指令中要使用两个文件寄存器。 这允许在两个寄存器之间直接移动数据，而不经过W寄存器。 从而提高性能并减少程序内存的使用。

    Microcontroller instruction set
    2.
    发明授权
    Microcontroller instruction set 有权
    微控制器指令集

    公开(公告)号：US07206924B2

    公开(公告)日：2007-04-17

    申请号：US10751210

    申请日：2003-12-31

    Applicant: Edward Brian Boles ,  Rodney Drake ,  Darrel Johansen ,  Sumit Mitra ,  Joseph Triece ,  Randy Yach

    Inventor： Edward Brian Boles ,  Rodney Drake ,  Darrel Johansen ,  Sumit Mitra ,  Joseph Triece ,  Randy Yach

    IPC: G06F12/08

    CPC classification number: G06F9/30192 ,  G06F9/30032 ,  G06F9/3004 ,  G06F9/30101 ,  G06F9/3012 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30167 ,  G06F9/321 ,  G06F9/325

    Abstract: A microcontroller apparatus is provided with an instruction set for manipulating the behavior of the microcontroller. The apparatus and system is provided that enables a linearized address space that makes modular emulation possible. Direct or indirect addressing is possible through register files or data memory. Special function registers, including the Program Counter (PC) and Working Register (W), are mapped in the data memory. An orthogonal (symmetrical) instruction set makes possible any operation on any register using any addressing mode. Consequently, two file registers to be used in some two operand instructions. This allows data to be moved directly between two registers without going through the W register. Thus increasing performances and decreasing program memory usage.

    Abstract translation: 微控制器装置设置有用于操纵微控制器的行为的指令集。 提供了使得能够实现模块化仿真的线性化地址空间的装置和系统。 可以通过寄存器文件或数据存储器进行直接或间接寻址。 特殊功能寄存器，包括程序计数器（PC）和工作寄存器（W），映射到数据存储器中。 正交（对称）指令集可以使用任何寻址模式对任何寄存器进行任何操作。 因此，在两个操作数指令中要使用两个文件寄存器。 这允许在两个寄存器之间直接移动数据，而不经过W寄存器。 从而增加性能并减少程序内存的使用。

    Method and apparatus for testing a relatively slow speed component of an intergrated circuit having mixed slow speed and high speed components
    3.
    发明授权
    Method and apparatus for testing a relatively slow speed component of an intergrated circuit having mixed slow speed and high speed components 失效
    用于测试具有混合的低速和高速分量的集成电路的相对较慢速度分量的方法和装置

    公开(公告)号：US5870409A

    公开(公告)日：1999-02-09

    申请号：US671011

    申请日：1996-06-28

    Applicant: Randy Yach ,  Rodney Drake

    Inventor： Randy Yach ,  Rodney Drake

    IPC: G01R31/00 ,  G02F1/13 ,  G02F1/133 ,  G06F11/267 ,  G09G3/00 ,  G09G3/36 ,  H04N5/66 ,  G01R31/28

    CPC classification number: G09G3/006 ,  G06F11/2221

    Abstract: A method is disclosed for testing a high speed microcontroller fabricated on a semiconductor chip, and for testing relatively low speed functions of a liquid crystal display (LCD) module on the chip that drives an off-chip LCD for an external system to be controlled by the microcontroller with a plurality of discrete analog voltage levels for performing the LCD functions. Digital values are multiplexed in time slots of a test waveform to simulate in high speed digital format of a test mode the low speed timing, relative magnitude and functionality of analog voltage levels used to drive the LCD; A high speed driver is selectively coupled to a pin of the chip, to which the discrete analog voltage levels are normally applied at low speed to drive the LCD, and the test waveform is applied to the high speed driver. The digital values and timing that appear on the pin are then monitored as an indication of proper functionality of the LCD module. The high speed driver is switched out and the normal low speed LCD driver is switched back for return to an LCD user mode when the test mode is completed. Monitoring the pin with a digital tester allows verification that pin pulses in predetermined time slots indicate the corresponding analog voltage level is being applied at the proper time during normal operation of the LCD module, and digitally testing of continuity in an analog channel. A transistor normally employed on the chip for electrostatic discharge protection is activated to selectively couple the high speed driver to the pin for the high speed testing mode.

    Abstract translation: 公开了一种用于测试在半导体芯片上制造的高速微控制器的方法，并且用于测试芯片上的液晶显示器（LCD）模块的相对低速功能，该芯片驱动用于外部系统的片外LCD以由 具有用于执行LCD功能的多个离散模拟电压电平的微控制器。 数字值在测试波形的时隙中进行多路复用，以模拟用于驱动LCD的模拟电压电平的低速定时，相对幅度和功能的测试模式的高速数字格式; 选择性地将高速驱动器耦合到芯片的引脚，通过低速驱动分立的模拟电压电平来驱动LCD，测试波形被施加到高速驱动器。 然后监视引脚上出现的数字值和时序作为LCD模块正常功能的指示。 当测试模式完成时，高速驱动器被切换并且正常的低速LCD驱动器被切回以返回到LCD用户模式。 使用数字测试仪监控引脚，可以验证在预定时隙内的引脚脉冲表示在LCD模块正常工作期间的适当时间正在施加相应的模拟电压电平，并对模拟通道的连续性进行数字测试。 通常在芯片上用于静电放电保护的晶体管被​​激活以选择性地将高速驱动器耦合到用于高速测试模式的引脚。

    Functional pathway configuration at a system/IC interface
    5.
    发明授权
    Functional pathway configuration at a system/IC interface 失效
    功能通道在系统/ IC接口配置

    公开(公告)号：US06552567B1

    公开(公告)日：2003-04-22

    申请号：US09964664

    申请日：2001-09-28

    Applicant: Brian Boles ,  Richard Fischer ,  Sumit Mitra ,  Rodney Drake ,  Stephen A. Bowling ,  Bryan Kris ,  Steven Marsh ,  Hassan Harb

    Inventor： Brian Boles ,  Richard Fischer ,  Sumit Mitra ,  Rodney Drake ,  Stephen A. Bowling ,  Bryan Kris ,  Steven Marsh ,  Hassan Harb

    IPC: H03K190175

    CPC classification number: G06F15/76

    Abstract: The present invention relates generally to functional pathway configurations at the interfaces between integrated circuits (ICs) and the circuit assemblies with which the ICs communicate. More particularly, the present invention relates generally to the functional pathway configuration at the interface between one or more semiconductor integrated circuit dice, including an IC package and the circuitry of a system wherein the integrated circuit dice is a digital signal controller. Even more particularly, the present invention relates to a 18, 28, 40, 44, 64 or 80 pin functional pathway configuration for the interface between the digital signal controller and the system in which it is embedded.

    Abstract translation: 本发明一般涉及集成电路（IC）与IC连接的电路组件之间的接口上的功能通路配置。 更具体地说，本发明一般涉及包括IC封装的一个或多个半导体集成电路管芯与系统的电路之间的界面处的功能通路配置，其中集成电路管芯是数字信号控制器。 更具体地，本发明涉及用于数字信号控制器和嵌入其中的系统之间的接口的18,28,40,44,64或80引脚功能通路配置。

    Microcontroller with LCD control over updating of RAM-stored data determines LCD pixel activation
    6.
    发明授权
    Microcontroller with LCD control over updating of RAM-stored data determines LCD pixel activation 失效
    具有LCD控制的微控制器可更新RAM存储数据，从而确定LCD像素激活

    公开(公告)号：US6031510A

    公开(公告)日：2000-02-29

    申请号：US671950

    申请日：1996-06-28

    Applicant: Rodney Drake ,  Scott Ellison

    Inventor： Rodney Drake ,  Scott Ellison

    IPC: G02F1/133 ,  G09G3/18 ,  G09G3/20 ,  G09G3/36

    CPC classification number: G09G3/18 ,  G09G2330/02

    Abstract: Method and apparatus for controlling the updating of a random access memory (RAM) that stores data for coding the activation of segments of one or more alphanmeric characters of a liquid crystal display (LCD), to maintain substantially a direct current (DC) voltage value of zero across transparent conductive plates of the LCD, is performed or provided in a microcontroller having internal LCD control capabilities. A type B waveform is employed for activating the LCD, the waveform being of a type in which data is transmitted over two frames, the data in the second frame of which is the inverse of data in the first frame thereof to maintain an average DC voltage value over each two-frame portion of the waveform at substantially zero volt. The RAM is allowed to be written to for updating the data therein only after completion of an entire two-frame portion of the waveform and before commencement of a new two-frame portion, to avoid a non-zero average DC voltage across the LCD glass during a two-frame portion. An error bit is set whenever an attempt is made to write to the RAM at times other than between the end of a two-frame portion and the commencement of a new two-frame portion. A response to the error bit is made by returning to the write step that prompted it, to determine whether all of the data intended to be written has been stored in the RAM.

    Abstract translation: 用于控制随机存取存储器（RAM）的更新的方法和装置，其存储用于对液晶显示器（LCD）的一个或多个字母字符的段的激活进行编码的数据，以维持基本上直流（DC）电压值 在LCD的透明导电板上的零位被执行或提供在具有内部LCD控制能力的微控制器中。 采用B型波形来激活LCD，该波形是数据在两帧上传输的类型，第二帧中的数据是其第一帧中的数据的倒数，以保持平均DC电压 波形的每个两帧部分基本上为零伏。 在完成波形的整个两帧部分之后并且在新的两帧部分开始之前，允许RAM被写入以用于更新其中的数据，以避免LCD玻璃上的非零平均DC电压 在两帧部分。 每当尝试在两帧部分的结束之前的时间和新的两帧部分的开始之间的时间尝试写入RAM时，设置错误位。 通过返回提示它的写入步骤来确定对错误位的响应，以确定所有要写入的数据是否已经存储在RAM中。

    Method for powering down unused configuration bits to minimize power consumption
    7.
    发明授权
    Method for powering down unused configuration bits to minimize power consumption 有权
    关闭未使用配置位以最小化功耗的方法

    公开(公告)号：US06463544B2

    公开(公告)日：2002-10-08

    申请号：US09850214

    申请日：2001-05-07

    Applicant: Joseph W. Triece ,  Rodney Drake ,  Igor Wojewoda

    Inventor： Joseph W. Triece ,  Rodney Drake ,  Igor Wojewoda

    IPC: G06F126

    CPC classification number: G11C5/14 ,  G11C7/1045 ,  H03K19/0016

    Abstract: A system for powering down configuration circuits to minimize power consumption has at least one first configuration circuit for configuring a peripheral module. A second configuration circuit is coupled to the peripheral module and to the at least one first configuration circuit. The second configuration circuit is used for enabling and disabling the peripheral module. The second configuration circuit is further used to power down the at least one first configuration circuit to minimize current consumption of the at least one first configuration circuit when the peripheral module is disabled.

    Abstract translation: 用于断电配置电路以最小化功耗的系统具有用于配置外围模块的至少一个第一配置电路。 第二配置电路耦合到外围模块和至少一个第一配置电路。 第二个配置电路用于启用和禁用外围模块。 当外围模块被禁用时，第二配置电路还用于断电至少一个第一配置电路以最小化至少一个第一配置电路的电流消耗。

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