公开(公告)号：US20180098420A1

公开(公告)日：2018-04-05

申请号：US15549107

申请日：2015-08-20

Applicant: Renesas Electronics Corporation

Inventor： Shuuichi KARIYAZAKI ,  Wataru SHIROI ,  Kenichi KUBOYAMA

IPC: H05K1/02 ,  H05K1/11 ,  H05K1/14 ,  H05K3/40

CPC classification number: H05K1/0248 ,  H01L23/32 ,  H01L25/04 ,  H01L25/18 ,  H01L2224/16225 ,  H05K1/0239 ,  H05K1/0243 ,  H05K1/0298 ,  H05K1/11 ,  H05K1/113 ,  H05K1/119 ,  H05K1/141 ,  H05K1/16 ,  H05K1/18 ,  H05K1/181 ,  H05K1/182 ,  H05K3/4046 ,  H05K7/02 ,  H05K2201/09218 ,  H05K2201/10378

Abstract: A semiconductor device according to an embodiment has a first semiconductor component and a second semiconductor component which are electrically connected with each other via an interposer. The interposer has a plurality of first signal wiring paths, and a plurality of second signal wiring paths each having a path distance smaller than each of the plurality of first signal wiring paths. Furthermore, the first semiconductor component includes a first electrode, a second electrode, and a third electrode arranged in order in a first direction. Furthermore, the second semiconductor component includes a fourth electrode, a fifth electrode, and a sixth electrode arranged in order in the first direction. Furthermore, the first electrode is connected with the fourth electrode via the first signal wiring path, the second electrode is connected with the fifth electrode via the first signal wiring path, and the third electrode is connected with the sixth electrode via the first signal wiring path.

公开(公告)号：US20160218083A1

公开(公告)日：2016-07-28

申请号：US14967463

申请日：2015-12-14

Applicant: Renesas Electronics Corporation

Inventor： Shuuichi KARIYAZAKI ,  Wataru SHIROI ,  Ryuichi OIKAWA ,  Kenichi KUBOYAMA

IPC: H01L25/065 ,  H01L23/498

CPC classification number: H01L25/0655 ,  H01L23/147 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/528 ,  H01L24/13 ,  H01L24/16 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/13022 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/3025 ,  H01L2924/0002 ,  H01L2924/00

Abstract: To improve reliability of signal transmission of an interposer which couples between semiconductor chips. A reference potential wiring and a reference potential wiring are provided on both neighboring sides of a signal wiring provided in a first wiring layer of an interposer. Also, a reference potential wiring and a reference potential wiring are provided on both neighboring sides of a signal wiring provided in a second wiring layer of the interposer. Further, the signal wiring and the signal wiring cross each other in plan view. The reference potential wirings of the first wiring layer, and the reference potential wirings of the second wiring layer are coupled to each other at the periphery of their crossing portion.

Abstract translation: 为了提高耦合在半导体芯片之间的插入器的信号传输的可靠性。 在设置在插入件的第一布线层中的信号线的两个相邻侧上设置参考电位布线和参考电位布线。 此外，在设置在插入器的第二布线层中的信号线的两个相邻侧上设置参考电位布线和参考电位布线。 此外，信号布线和信号布线在平面图中彼此交叉。 第一布线层的参考电位布线和第二布线层的参考电位布线在其交叉部分的周围彼此耦合。